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ISL23318TFUZ Folha de dados(PDF) 7 Page - Intersil Corporation |
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ISL23318TFUZ Folha de dados(HTML) 7 Page - Intersil Corporation |
7 / 19 page ISL23318 7 FN7887.0 July 26, 2011 Serial Interface Specification For SCL, SDA, A0, A1 unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis VLOGIC > 2V 0.05 x VLOGIC V VLOGIC < 2V 0.1 x VLOGIC VOL SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V Cpin SDA, SCL Pin Capacitance 10 pF fSCL SCL Frequency 400 kHz tsp Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VLOGIC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VLOGIC crossing 600 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC 600 ns tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VCC to SDA entering the 30% to 70% of VLOGIC window 0ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC 600 ns tHD:STO STOP Condition Hold Time for Read or Write From SDA rising edge to SCL falling edge; both crossing 70% of VLOGIC 1300 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL =3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V 0ns tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns |
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Descrição semelhante - ISL23318TFUZ |
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