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GS1540-CQR Folha de dados(PDF) 11 Page - Gennum Corporation |
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GS1540-CQR Folha de dados(HTML) 11 Page - Gennum Corporation |
11 / 17 page GENNUM CORPORATION 522 - 27 - 03 11 of 17 Fig. 13 PCLK Output Circuit Fig. 14 DDO_EN Circuit Fig. 15 Serial (DDO) Output Stage Circuit DETAILED DESCRIPTION The GS1540 is a single standard receiver for serial digital HDTV signals at 1.485Gb/s and 1.485/1.001Gb/s. UNIQUE SLEW PHASE LOCK LOOP (S-PLL): A unique feature of the GS1540 is the innovative slew phase lock loop (S-PLL). When a step phase change is applied to the PLL, the output phase gains constant rate of change with respect to time. This behaviour is termed slew. Figure 16 shows an example of input and output phase variation over time for slew and linear (conventional) PLLs. Since the slewing is a nonlinear behavior, the small signal analysis cannot be done in the same way as the standard PLL. However, it is still possible to plot input jitter transfer characteristics at a constant input jitter modulation. Fig. 16 PLL Characteristics Slew PLLs offer several advantages such as excellent noise immunity. Because of the infinite bandwidth for an infinitely small input jitter modulation (or jitter introduced by VCO), the loop corrects for that immediately thus the small signal noise of the VCO is cancelled. The GS1540 uses a very clean, external VCO called the GO1515 (refer to the GO1515 Data Sheet for details). In addition, the bi-level digital phase detector provides constant loop bandwidth that is predominantly independent of the data transition density. The loop bandwidth of a conventional tri-stable charge pump drops with reducing data transitions. During pathological signals, the data transition density reduces from 0.5 to 0.05, but the slew PLL’s performance essentially remains unchanged. PCLK_VEE PCLK_VCC 27k 100 PCLK DDO_VEE DDO_VCC 2k 20k DDO_EN 50 50 DDO DDO DDO_VEE zDDO_VCC 0.2 0.1 0.0 INPUT OUTPUT SLEW PLL RESPONSE 0.2 0.1 0.0 INPUT OUTPUT LINEAR (CONVENTIONAL) PLL RESPONSE |
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Descrição semelhante - GS1540-CQR |
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