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5V925BQGI Folha de dados(PDF) 11 Page - Integrated Device Technology

Nome de Peças 5V925BQGI
Descrição Electrónicos  Programmable LVCMOS/LVTTL Clock Generator
Download  18 Pages
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Fabricante Electrônico  IDT [Integrated Device Technology]
Página de início  http://www.idt.com
Logo IDT - Integrated Device Technology

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IDT5V925BQGI REVISION B JANUARY 21, 2011
11
©2011 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Schematic Examples, continued
Figure 4B. IDT5V925BI Application Schematic with LVCMOS Reference Clock Input
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Zo = 50 Ohm
To Logic
Input
pins
C6
0.1uF
Logic Control Input Examples
C7
0.1uF
RD2
1K
3.3V
C3
0.1uF
BLM18BB221SN2
Ferrite Bead
1
2
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S1
S0
GNDQ
VDDQ
X1
X2
CLKIN
FB
/OE
GND
Q/N
Q0
Q1
Q2
GND
VDD
VDDQ
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
VDD=3.3V
RU1
1K
Set Logic
Input to
'1'
R2
33
VDD
C5
10uF
Zo = 50 Ohm
VDDQ=3.3V
R3
100
VDDQ
To Logic
Input
pins
BLM18BB221SN1
Ferrite Bead
1
2
Q0
Q1
RU2
Not Install
Ro ~ 7 Ohm
Q1
Driv er_LVCMOS
S1
/OE
Q/N
Zo = 50 Ohm
LVCMOS
Optional Termination
VDD
VDD
R1
33
R4
100
VDD
LVCMOS
C8
10uF
Q2
RD1
Not Install
Set Logic
Input to
'0'
3.3V
S2
R5
43
C4
0.1uF


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