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AZT70 Folha de dados(PDF) 7 Page - Arizona Microtek, Inc |
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AZT70 Folha de dados(HTML) 7 Page - Arizona Microtek, Inc |
7 / 12 page Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC www.azmicrotek.com +1-480-962-5881 7 Request a Sample May 2012, Rev 1.2 t DA CLK bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 0 loaded 1st bit 10 loaded last PV 4µs min 10ms min ≥5.6V, ≤6.1V Figure 8 – First programming cycle to program bit2 into the EEPROM t DA CLK bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 0 loaded 1st bit 10 loaded last PV 4µs min 10ms min ≥5.6V, ≤6.1V Figure 9 – Second programming cycle to program bit4 into the EEPROM READING BACK FROM THE EEPROM During programming, the PV pin is used to program the necessary control bits into the EEPROM. However, it is also used to read the bits currently programmed into the EEPROM. When the PV pin is not used during programming, the AZT70 provides a weak pull-up and pull-down on the pin. This allows the EEPROM data to be shifted out to the PV pin and read after the CLK sequence is complete and when the DA & CLK pins are high (Figure 10). Each EEPROM bit is selected by setting the DA signal low (EEPROM selection is active low) during the CLK sequence. With an external 68kΩ resistor pull-up to VDD on the PV pin, a low EEPROM bit produces ≤ 0.4V level while a high EEPROM bit produces a ≥ 0.6*V DD level. |
Nº de peça semelhante - AZT70 |
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Descrição semelhante - AZT70 |
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