DAC902

3

SBAS094B

DAC902U/E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE (Cont.)

to 0.1%

30

ns

10% to 90%

2

ns

10% to 90%

2

ns

Glitch Impulse

3pV-s

DC-ACCURACY

2.0

20.0

mA

Output Compliance Range

–1.0

+1.25

V

Gain Error

With Internal Reference

–10

±1

+10

%FSR

Gain Error

With External Reference

–10

±2

+10

%FSR

Gain Drift

With Internal Reference

±120

ppmFSR/

°C

Offset Error

With Internal Reference

–0.025

+0.025

%FSR

Offset Drift

With Internal Reference

±0.1

ppmFSR/

°C

–0.2

+0.2

%FSR/V

–0.025

+0.025

%FSR/V

Output Noise

50

pA/

√Hz

Output Resistance

200

k

Ω

Output Capacitance

12

pF

REFERENCE

Reference Voltage

+1.24

V

Reference Tolerance

±5%

Reference Voltage Drift

±50

ppmFSR/

°C

Reference Output Current

10

µA

Reference Input Resistance

1M

Ω

Reference Input Compliance Range

0.1

1.25

V

1.3

MHz

DIGITAL INPUTS

Logic Coding

Straight Binary

Latch Command

Rising Edge of Clock

3.5

5

V

0

1.2

V

2

3

V

0

0.8

V

±20

µA

±20

µA

Input Capacitance

5pF

POWER SUPPLY

Supply Voltages

+2.7

+5

+5.5

V

+2.7

+5

+5.5

V

24

30

mA

1.1

2

mA

815

mA

Power Dissipation

170

230

mW

50

mW

Power Dissipation, Power-Down Mode

45

mW

Thermal Resistance,

θ

JA

SO-28

75

°C/W

TSSOP-28

50

°C/W

Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45

µA for the PD pin, which has an