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TMP101NAQDBVRQ1 Folha de dados(PDF) 10 Page - Texas Instruments

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Nome de Peças TMP101NAQDBVRQ1
Descrição Electrónicos  DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
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TMP100-Q1
TMP101-Q1
SBOS581
– SEPTEMBER 2011
www.ti.com
All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for
all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is
configured for 9-bit resolution.
SERIAL INTERFACE
The TMP100-Q1 and TMP101-Q1 operate only as slave devices on the I2C bus and SMBus. Connections to the
bus are made via the open-drain I/O lines SDA and SCL. The TMP100-Q1 and TMP101-Q1 support the
transmission protocol for fast (up to 400 kHz) and high-speed (up to 3.4 MHz) modes. All data bytes are
transmitted most significant bit first.
SERIAL BUS ADDRESS
To program the TMP100-Q1 and TMP101-Q1, the master must first address slave devices via a slave address
byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing
a read or write operation. The TMP100-Q1 features two address pins to allow up to eight devices to be
addressed on a single I2C interface. Table 11 describes the pin logic levels used to properly connect up to eight
devices. Float indicates the pin is left unconnected. The state of pins ADD0 and ADD1 is sampled on the first I2C
bus communication and should be set prior to any activity on the interface.
Table 11. Address Pins and Slave Addresses for the
TMP100-Q1
ADD1
ADD0
SLAVE ADDRESS
0
0
1001000
0
Float
1001001
0
1
1001010
1
0
1001100
1
Float
1001101
1
1
1001110
Float
0
1001011
Float
1
1001111
The TMP101-Q1 features one address pin and an ALERT pin, allowing up to three devices to be connected per
bus. Pin logic levels are described in Table 12. The address pins of the TMP100-Q1 and TMP101-Q1 are read
after reset or in response to an I2C address acquire request. Following reading, the state of the address pins is
latched to minimize power dissipation associated with detection.
The TMP101-Q1 features one address pin and an ALERT pin, allowing up to three devices to be connected per
bus. Pin logic levels are described in Table 12. The address pins of the TMP100-Q1 and TMP101-Q1 are read
after reset or in response to an I2C address acquire request. Following reading, the state of the address pins is
latched to minimize power dissipation associated with detection.
Table 12. Address Pins and Slave Addresses for the
TMP101-Q1
ADD0
SLAVE ADDRESS
0
1001000
Float
1001001
1
1001010
BUS OVERVIEW
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions
10
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Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): TMP100-Q1 TMP101-Q1


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