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74HCT573-Q100 Folha de dados(PDF) 9 Page - NXP Semiconductors |
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74HCT573-Q100 Folha de dados(HTML) 9 Page - NXP Semiconductors |
9 / 19 page 74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 16 August 2012 9 of 19 NXP Semiconductors 74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD =CPD VCC2 fi N+ (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (C L VCC 2 f o) = sum of outputs. For type 74HCT573-Q100 tpd propagation delay Dn to Qn; see Figure 7 [1] VCC = 4.5 V - 20 35 - 44 - 53 ns VCC =5V; CL =15pF - 17 - - - - - ns tpd propagation delay LE to Qn; see Figure 8 [1] VCC = 4.5 V - 18 35 - 44 - 53 ns VCC =5V; CL =15pF - 15 - - - - - ns ten enable time OE to Qn; see Figure 9 [2] VCC = 4.5 V - 17 30 - 38 - 45 ns tdis disable time OE to Qn; see Figure 9 [3] VCC = 4.5 V - 18 30 - 38 - 45 ns tt transition time Qn; see Figure 7 [4] VCC = 4.5 V - 5 12 - 15 - 18 ns tW pulse width LE HIGH; see Figure 8 VCC = 4.5 V 16 5 - 20 - 24 - ns tsu set-up time Dn to LE; see Figure 10 VCC = 4.5 V 13 7 - 16 - 20 - ns th hold time Dn to LE; see Figure 10 VCC = 4.5 V 9 4 - 11 - 15 - ns CPD power dissipation capacitance CL =50pF;f= 1 MHz; VI =GND to VCC [5] -26 - - - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max |
Nº de peça semelhante - 74HCT573-Q100 |
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Descrição semelhante - 74HCT573-Q100 |
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