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LC75810E Folha de dados(PDF) 10 Page - Sanyo Semicon Device

Nome de Peças LC75810E
Descrição Electrónicos  1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers
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Fabricante Electrônico  SANYO [Sanyo Semicon Device]
Página de início  https://www.sanyo-av.com/us/
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LC75810E/T
No.7141-10/54
CGROM (Character generator ROM)
CGROM is the ROM that is used to generate the 240 kinds of 5
× 7, 5 × 8, or 5 × 9 dot matrix character patterns from
the 8-bit character codes. CGROM has a capacity of 240
× 45 bits. When a character code is written to DCRAM, the
character pattern stored in the CGROM corresponding to the character code is displayed at the position on the LCD
corresponding to the DCRAM address loaded into AC.
CGRAM (Character generator RAM)
CGRAM is the RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5
× 7, 5 ×
8, or 5
× 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits.
ALATCH (Additional data latch)
ALATCH is the latch that is used to store the ADATA display data for the accessory display. ALATCH has a capacity
of 80 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM.
SC (Scroll counter)
SC is the counter that is used to scroll the display in the left, right, up, or down directions in dot units. Since this
function scrolls in dot units, it implements smooth scrolling.
Reset Function
The LC75810E and LC75810T are reset when a low level is applied to the RES pin at power on and, in normal mode. On a
reset the LC75810E and LC75810T create a display with all LCD panels turned off. However, after a reset applications
must set the contents of DCRAM, ALATCH, and CGRAM before turning on display with a “display on/off control”
instruction since the contents of these memories are undefined. That is, applications must execute the following
instructions.
Set display technique
DCRAM data write
ALATCH data write (If ALATCH is used.)
CGRAM data write (IF CGRAM is used.)
Set AC and SC addresses
Set display contrast (If the display contrast adjustment circuit is used.)
After executing the above instructions, applications must turn on the display with a “display on/off control” instruction.
Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off
control” instruction. (See the detailed instruction descriptions.)
Serial Data Transfer Format
When CL is stopped at the low level
Instruction data
Up to 144 bits
CCB address
8 bits
A3
A2
A1
A0
B3
B2
D143
D142
D4
D3
D2
10
0
0
1
1
1
0D0
D1
B1
CE
DI
CL
B0
When CL is stopped at the high level
Instruction data
Up to 144 bits
CCB address
8 bits
A3
A2
A1
A0
B3
B2
D143
D142
D4
D3
D2
0
0
0
11
1
1
0
D0 D1
B1
CE
DI
CL
B0
CCB address: 4EH
D0 to D143: Instruction data
The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When
transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one
set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.


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