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AD1853JRSRL Folha de dados(PDF) 3 Page - Analog Devices |
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AD1853JRSRL Folha de dados(HTML) 3 Page - Analog Devices |
3 / 16 page REV. A –3– AD1853 POWER Min Typ Max Units Supplies Voltage, Analog and Digital 4.5 5 5.5 V Analog Current 12 15 mA Digital Current 28 33 mA Dissipation Operation—Both Supplies 200 mW Operation—Analog Supply 60 mW Operation—Digital Supply 140 mW Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins –77 dB 20 kHz 300 mV p-p Signal at Analog Supply Pins –72 dB Specifications subject to change without notice. TEMPERATURE RANGE Min Typ Max Units Specifications Guaranteed 25 °C Functionality Guaranteed 0 70 °C Storage –55 125 °C Specifications subject to change without notice. DIGITAL FILTER CHARACTERISTICS Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB) 44.1 DC–20 24.1–328.7 110 ±0.0002 48 DC–21.8 26.23–358.28 110 ±0.0002 96 DC–39.95 56.9–327.65 115 ±0.0005 192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz) +0/–0.5 (DC–65.4 kHz) +0/–1.5 (DC–87.2 kHz) Specifications subject to change without notice. GROUP DELAY Chip Mode Group Delay Calculation FS Group Delay Units INT8x Mode 5553/(128 × FS) 48 kHz 903.8 µs INT4x Mode 5601/(64 × F S) 96 kHz 911.6 µs INT2x Mode 5659/(32 × FS) 192 kHz 921 µs Specifications subject to change without notice. DIGITAL TIMING (Guaranteed Over 0 C to +70 C, AVDD = DVDD = +5.0 V 10%) Min Units tDMP MCLK Period (With FMCLK = 256 × F LRCLK)* 54 ns tDML MCLK LO Pulsewidth (All Modes) 0.4 × tDMP ns tDMH MCLK HI Pulsewidth (All Modes) 0.4 × tDMP ns tDBH BCLK HI Pulsewidth 20 ns tDBL BCLK LO Pulsewidth 20 ns tDBP BCLK Period 140 ns tDLS LRCLK Setup 20 ns tDLH LRCLK Hold (DSP Serial Port Mode Only) 5 ns tDDS SDATA Setup 5 ns t DDH SDATA Hold 10 ns t PDRP PD/RST LO Pulsewidth 5 ns *Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature. Specifications subject to change without notice. |
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