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AD1855JRSRL Folha de dados(PDF) 8 Page - Analog Devices

Nome de Peças AD1855JRSRL
Descrição Electrónicos  Stereo, 96 kHz, Multibit DAC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD1855JRSRL Folha de dados(HTML) 8 Page - Analog Devices

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AD1855
REV. B
–8–
Serial Control Port
The AD1855 serial control port is SPI compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft power-down control, soft de-emphasis, channel-
specific attenuation and mute (both channels at once). The
AD1855 serial control port consists of three signals, control
clock CCLK (Pin 4), control data CDATA (Pin 5), and control
latch CLATCH (Pin 3). The control data input must be valid
on the control clock rising edge, and the control clock must
make a LO to HI transition when there is valid data. The con-
trol latch must make a LO to HI transition after the LSB has
been clocked into the AD1855, while the control clock is inac-
tive. The timing relation between these signals is shown in Fig-
ure 6. The control bits are assigned as in Table III.
Digital Timing
Min
Unit
tCCH
CCLK HI Pulsewidth
40 (Burst Mode)
ns
tCD
CCLK LO Pulsewidth
40 (Burst Mode)
ns
tCCP
CCLK Period
80 (Burst Mode)
ns
tCCSU CCLK Setup Time
100
ns
tCSU
CDATA Setup Time
10
ns
tCHD CDATA Hold Time
10
ns
tCLL
CLATCH LO Pulsewidth
10
ns
tCLH
CLATCH HI Pulsewidth
130
ns
tCLSU CLATCH HI Setup
130
ns
Table III. Serial Control Bit Definitions
MSB
LSB
Data 15 Data 14
Data 13 Data 12
Data 11
Data 10 Data 9
Data 8
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
IDPM1
IDPM0
Soft
Soft
1/Mute
1/Right
Volume Volume
Volume
Volume
Volume
Volume
Volume
Volume
Volume Volume
Input
Input
Power-
De-
0/Normal
0/Left
Control Control
Control
Control
Control
Control
Control
Control
Control Control
Mode1
Mode0
Down
Emphasis (Nonmute)
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Select
Select
tCLL
tCLSU
tCCH
tCSU
tCCL
tCHD
D15
D14
CDATA
CCLK
CLATCH
D0
tCLH
tCCSU
tCCP
Figure 6. Serial Control Port Timing
The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is one control register for the left chan-
nel or the right channel, as distinguished by bit Data 10. For
power-up and reset, the default settings are: Data 11 the Mute
control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through Vol-
ume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenua-
tion). The intent with these reset defaults is to enable AD1855
applications without requiring the use of the serial control port.
For those users who do not use the serial control port, it is still
possible to mute the AD1855 output by using the MUTE (Pin
23) signal.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/
RCLK after the
CLATCH write pulse as shown in Figure 7.
Mute
The AD1855 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Data 11) HI. The
AD1855 has been designed to minimize pops and clicks when
muting and unmuting the device.


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