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AD1876JN Folha de dados(PDF) 5 Page - Analog Devices

Nome de Peças AD1876JN
Descrição Electrónicos  16-Bit 100 kSPS Sampling ADC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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AD1876
REV. A
–5–
PIN DESCRIPTION
Pin
No.
Name
Type
Description
1
SAMPLE
DI
VIN Acquisition Control Pin. During conversion, SAMPLE controls the state of the internal
Sample-Hold Amplifier and initiates conversion (see “Conversion Control” paragraph). Dur-
ing calibration, SAMPLE is active HIGH, forcing DOUT (Pin 3) LOW. If SAMPLE is LOW
during calibration, DOUT will output diagnostic information (See “Autocalibration” paragraph.)
2
CLK
DI
Master Clock Input. The AD1876 requires 17 clock pulses to execute a conversion. CLK is
also used to derive DOUT CLK (Pin 14). During calibration, 5000 clock pulses are applied.
3DOUT
DO
Serial Output Data, Twos Complement format.
4
DGND
P
Digital Ground.
5VCC
P
+12 V Analog Supply Voltage.
6
N/C
No Connection.
7
N/C
No Connection.
8
AGND
P/AI
Analog Ground.
9
AGND SENSE
AI
Analog Ground Sense.
10
VIN
AI
Analog Input Voltage, referred the AGND SENSE.
11
VREF
AI
External Voltage Reference Input, referred to AGND.
12
VEE
P
–12 V Analog Supply Voltage.
13
VDD
P
+5 V Logic Supply Voltage.
14
DOUT CLK
DO
The rising edge of DOUT CLK may be used to latch DOUT (Pin 3). DOUT CLK is derived from
CLK.
15
BUSY
DO
Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.
16
CAL
DI
Calibration Control Pin (asynchronous).
Type:
AI = Analog Input.
DI = Digital Input.
DO = Digital Output.
P = Power.
AGND
V
REF
COMP
A CHIP
VIN
8
10
11
9
LEVEL TRANSLATORS
LOGIC TIMING
16-BIT
DAC
INPUT
BUFFERS
CAL
DAC
CLK
SAMPLE
D
CLK
OUT
D CHIP
DOUT
3
14
AD1876
2
16
1
RAM
ALU
SAR
AGND SENSE
CAL
15 BUSY
MICROCODED
CONTROLLER
Functional Block Diagram
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD1876
NC = NO CONNECT
SAMPLE
VDD
DOUTCLK
BUSY
CAL
CLK
DOUT
DGND
VIN
VREF
VEE
VCC
NC
NC
AGND
AGND SENSE
Package Pinout


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