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AD5280BRU20 Folha de dados(PDF) 5 Page - Analog Devices |
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AD5280BRU20 Folha de dados(HTML) 5 Page - Analog Devices |
5 / 10 page PRELIMINARY TECHNICAL DATA AD5280/AD5282 REV PrE 12 MAR 02 5 Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com TABLE 2: AD5282 PIN Function Descriptions Pin Name Description 1 O1 Logic Output terminal O1 2 A1 Resistor terminal A1 3 W1 Wiper terminal W1 4 B1 Resistor terminal B1 5 VDD Positive power supply, specified for operation from +5 to +15V. 6 SHDN Active Low, Asynchronous connection of the wiper W to terminal B, and open circuit of terminal A. RDAC register contents unchanged. 7 SCL Serial Clock Input 8 SDA Serial Data Input/Output 9 AD0 Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses. 10 AD1 Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses. 11 GND Common Ground 12 VSS Negative power supply, specified for operation from 0 to -5V 13 VL Logic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5282. 14 B2 Resistor terminal B2 15 W2 Wiper terminal W2 16 A2 Resistor terminal A2 t 4 SDA SCL PS Sr P t 1 t 2 t 3 t 5 t 6 t 7 t 8 t 8 t 9 t 10 Figure 1. Detail Timing Diagram Data of AD5280/AD5282 is accepted from the I 2C bus in the following serial format: S 0 1 0 1 1 A D 1 A D 0 R/ W W W W A A AA A/ B R S S D O 1 O 2 X X X A D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A P Slave Address Byte Instruction Byte Data Byte Where: S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care AD1, AD0 = Package pin programmable address bits R/ W W W W= Read Enable at High and Write Enable at Low A AA A/B = RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2 SD = Shutdown, same as SHDN pin operation except inverse logic O2, O1 = Output logic pin latched values D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits SCL SDA 1 9 1 0 1 1 0 AD0 AD1 R/ W ACK. BY AD5280 D7 D6 D5 D3 D4 D0 D1 D2 1 9 ACK. BY AD5280 A/ B RS S D O2 O1 X X X 1 9 ACK. BY AD5280 FRAME 1 Slave Address Byte START BY MAS TER FRA ME 2 Instruction Byte FRAME 3 Data B yte Figure 2. Writing to the RDAC Register |
Nº de peça semelhante - AD5280BRU20 |
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Descrição semelhante - AD5280BRU20 |
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