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AD557JN Folha de dados(PDF) 3 Page - Analog Devices |
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AD557JN Folha de dados(HTML) 3 Page - Analog Devices |
3 / 4 page AD557 REV.A –3– Figure 1. Functional Block Diagram The high-speed output buffer amplifier is operated in the noninverting mode with gain determined by the user- connections at the output range select pin. The gain-setting application resistors are thin film laser trimmed to match and track the DAC resistors and to assure precise initial calibration of the output range, 0 V to 2.56 V. The amplifier output stage is an NPN transistor with passive pull-down for zero-based output capability with a single power supply. The internal precision voltage reference is of the patented band-gap type. This design produces a reference voltage of 1.2 V and thus, unlike 6.3 V temperature-compensated Zeners, may be operated from a single, low-voltage logic power supply. The microprocessor interface logic consists of an 8-bit data latch and control circuitry. Low power, small geometry and high speed are advantages of the I 2L design as applied to this section. I 2L is bipolar process compatible so that the performance of the analog sections need not be compromised to provide on-chip logic capabilities. The control logic allows the latches to be operated from a decoded microprocessor address and write sig- nal. If the application does not involve a µP or data bus, wiring CS and CE to ground renders the latches “transparent” for direct DAC access. Digital Input Code Output Binary Hexadecimal Decimal Voltage 0000 0000 00 0 0 0000 0001 01 1 0.010 V 0000 0010 02 2 0.020 V 0000 1111 0F 15 0.150 V 0001 0000 10 16 0.160 V 0111 1111 7F 127 1.270 V 1000 0000 80 128 1.280 V 1100 0000 C0 192 1.920 V 1111 1111 FF 255 2.55 V CONNECTING THE AD557 The AD557 has been configured for low cost and ease of appli- cation. All reference, output amplifier and logic connections are made internally. In addition, all calibration trims are performed at the factory assuring specified accuracy without user trims. The only connection decision to be made by the user is whether the output range desired is unipolar or bipolar. Clean circuit board layout is facilitated by isolating all digital bit inputs on one side of the package; analog outputs are on the opposite side. UNIPOLAR 0 V TO +2.56 V OUTPUT RANGE Figure 2 shows the configuration for the 0 V to +2.56 V full- scale output range. Because of its precise factory calibration, the AD557 is intended to be operated without user trims for gain and offset; therefore, no provisions have been made for such user trims. If a small increase in scale is required, however, it may be accomplished by slightly altering the effective gain of the output buffer. A resistor in series with VOUT SENSE will increase the output range. Note that decreasing the scale by put- ting a resistor in series with GND will not work properly due to the code-dependent currents in GND. Adjusting offset by injecting dc at GND is not recommended for the same reason. Figure 2. 0 V to 2.56 V Output Range BIPOLAR –1.28 V TO +1.28 V OUTPUT RANGE The AD557 was designed for operation from a single power supply and is thus capable of providing only a unipolar 0 V to +2.56 V output range. If a negative supply is available, bipolar output ranges may be achieved by suitable output offsetting and scaling. Figure 3 shows how a ±1.28 V output range may be achieved when a –5 V power supply is available. The offset is provided by the AD589 precision 1.2 V reference which will operate from a +5 V supply. The AD711 output amplifier can provide the necessary ±1.28 V output swing from ±5 V supplies. Coding is complementary offset binary. Figure 3. Bipolar Operation of AD557 from ±5 V Supplies Applications GROUNDING AND BYPASSING All precision converter products require careful application of good grounding practices to maintain full rated performance. Because the AD557 is intended for application in microcom- puter systems where digital noise is prevalent, special care must be taken to assure that its inherent precision is realized. The AD557 has two ground (common) pins; this minimizes ground drops and noise in the analog signal path. Figure 4 shows how the ground connections should be made. It is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common in one place only. If the common tie-point is remote and accidental disconnection of that one common tie-point occurs due to card removal with power on, a large differential voltage between the |
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