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AD7011ARS Folha de dados(PDF) 3 Page - Analog Devices |
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AD7011ARS Folha de dados(HTML) 3 Page - Analog Devices |
3 / 12 page AD7011 REV. B –3– 20k 20k 20pF 20pF AD7011 ITx/QTx ITx / QTx 40k Ω Ω Ω Figure 1. Analog Output Test Load Circuit MASTER CLOCK TIMING Parameter Limit at TA = –40 C to +85 C Units Description t1 300 ns min MCLK Cycle Time t2 100 ns min MCLK High Time t3 100 ns min MCLK Low Time (VAA = VDD = +5 V 10%; AGND = DGND = 0 V. All specifications are TMIN to TMAX unless otherwise noted.) TO OUTPUT PIN +2.1V I OH C L 100pF 1.6mA 200µA I OL Figure 3. Load Circuit for Digital Outputs MCLK t 2 t 1 t 3 Figure 2. Master Clock (MCLK) Timing |
Nº de peça semelhante - AD7011ARS |
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Descrição semelhante - AD7011ARS |
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