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74ACTQ652SPC Folha de dados(PDF) 5 Page - Fairchild Semiconductor

Nome de Peças 74ACTQ652SPC
Descrição Electrónicos  Quiet Series??Transceiver/Register
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74ACTQ652SPC Folha de dados(HTML) 5 Page - Fairchild Semiconductor

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DC Electrical Characteristics (Continued)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: PDIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 7: Max number of data inputs (n) switching. (n
− 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD),
0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics
Note 8: Voltage Range 5.0 is 5.0V
± 0.5V.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any separate outputs of the same device. The spec-
ification applies to any output switching in the same direction, either HIGH-to-LOW (TOSHL) or LOW-to-HIGH (TOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
VCC
TA = +25°CTA = −40°C to +85°C
Units
Conditions
(V)
Typ
Guaranteed Limits
VILD
Maximum LOW Level
5.0
1.2
0.8
V
(Note 5)(Note 7)
Dynamic Input Voltage
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
fMAX
Maximum Clock Frequency
5.0
MHz
tPLH
Propagation Delay
5.0
2.0
7.0
9.5
2.0
10.0
ns
tPHL
Clock to Bus
tPLH
Propagation Delay
5.0
2.0
6.5
9.0
2.0
9.5
ns
tPHL
Bus to Bus
tPLH
Propagation Delay
5.0
2.5
6.5
10.0
2.5
10.5
ns
tPHL
SBA or SAB to A or B
tPZH
Enable Time
5.0
2.0
7.0
10.5
2.0
11.0
tPZL
OEBA to A (Note 8)
tPHZ
Disable Time
5.0
1.0
5.0
8.0
1.0
8.5
ns
tPLZ
OEBA to A (Note 8)
tPZH
Enable Time
5.0
2.0
7.0
10.5
2.0
11.0
tPZL
OEAB to B
tPHZ
Disable Time
5.0
1.0
5.0
8.0
1.0
8.5
ns
tPLZ
OEAB to B
ts(H)
Setup Time, HIGH or
5.0
3.0
3.0
ns
ts(L)
LOW, Bus to Clock
th(H)
Hold Time, HIGH or
5.0
1.5
1.5
ns
th(L)
LOW, Bus to Clock
tw(H)
Clock Pulse Width
5.0
4.0
4.0
ns
tw(L)
HIGH or LOW
tOSHL
Output to Output Skew (Note 9)
tOSLH
A to B, B to A or
5.0
0.5
1.0
1.0
ns
Clock to Output
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
54
pF
VCC = 5.0V


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