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TS34118CS28C8 Folha de dados(PDF) 8 Page - Taiwan Semiconductor Company, Ltd |
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TS34118CS28C8 Folha de dados(HTML) 8 Page - Taiwan Semiconductor Company, Ltd |
8 / 21 page TS34118 Voice Switched Speakerphone Circuit 8/21 Version: A13 Application Information (Continue) Attenuators The attenuators are controlled by the single output of the Control Block, which is measurable at the CT pin (pin 14). When the CT pin is at +240 millivolts with respect to VB, the circuit is in the receive mode (receive attenuator is at +6.0dB). When the CT voltage is at +240 millivolts with respect to VB, the circuit is in the transmit mode (transmit attenuator is at +6.0dB). The circuit is in an idle mode when the CT voltage is equal to VB. Causing the attenuators gain to be halfway between their fully on and fully off positions (-20dB each). Monitoring the CT voltage (with respect to VB) is the most direct method of monitoring the circuit’s mode. The inputs to the Control Block are seven, 2 from the comparators operated by the level detectors, 2 from the background noise monitors, the volume control, the dial-tone detector, and the AGC circuit. These seven inputs are described below. Level Detectors There are four level detectors-two on the receive side and two on the transmit side. Refer to Figure 4. The terms in parentheses from one system, and the other terms from one system. Each level detector is a high gain amplifier with back-to-bank diodes in the feedback path, resulting in non-linear gain, which permits operation over a wide dynamic range of speech levels. The sensitivity of each level detector is determined by the external resistor and capacitor at each input (TLI1, TLI2, RLI1 and RLI2). Each output charge an external capacitor through a diode and limiting resistor, thus providing a do representation of the input as signal level. The outputs have a quick rise time (determined by the capacitor and an internal 350 ς resistor), and a slow decay time set by an internal current source and the capacitor. The capacitors on the four outputs should have the same value (±10%) to prevent timing problems. Referring to Figure 2, on the receives side, one level detector (RLI1) is at the receive input receiving thus same signal as at Tip and Ring, and the other (PLI2) is at the output of the speaker amplifier. On the transmit side, one level detector (TLI2) is at the output of the microphone amplifier, while the other (TLI1) is at the hybrid output. Outputs RLO1 and TLO1 feed a comparator, the output of which goes to the Attenuator Control Block. Likewise, outputs RLO2 and TLO2 feed a second comparator which also goes to the Attenuator Control Block. The touch table for the effects of the level detectors on the Control Block is given in the section describing the Control Block. Figure 4. Level Detector |
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