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74VCX16835GX Folha de dados(PDF) 2 Page - Fairchild Semiconductor |
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74VCX16835GX Folha de dados(HTML) 2 Page - Fairchild Semiconductor |
2 / 10 page www.fairchildsemi.com 2 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Table H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 4: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 5: Output level before the indicated steady-state input conditions were established. Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input I1 - I18 Data Inputs O1 - O18 3-STATE Outputs NC No Connect 1 234 56 A O2 O1 NC GND I1 I2 B O4 O3 NC NC I3 I4 C O6 O5 VCC VCC I5 I6 D O8 O7 GND GND I7 I8 E O10 O9 GND GND I9 I10 F O12 O11 GND GND I11 I12 G O14 O13 VCC VCC I13 I14 H O16 O15 OE CLK I15 I16 J O17 O18 LE GND I18 I17 Inputs Outputs OE LE CLK In On HX X X Z LH X L L LH X H H LL ↑ LL LL ↑ HH LL H X O0 (Note 4) LL L X O0 (Note 5) |
Nº de peça semelhante - 74VCX16835GX |
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Descrição semelhante - 74VCX16835GX |
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