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ISLA212P20 Folha de dados(PDF) 9 Page - Intersil Corporation

Nome de Peças ISLA212P20
Descrição Electrónicos  Ultra High Performance Broadband 12 to 16-Bit Data Acquisition Platform
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA212P20 Folha de dados(HTML) 9 Page - Intersil Corporation

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Application Note 1837
9
AN1837.0
May 3, 2013
The ADC also can be used to measure the signal path frequency
response by holding a constant input power while stepping the
frequency and recording the change in the dBFS out of the FFT.
This is shown on a linear frequency scale in Figure 12 targeting a
single tone at -12dBFS out of the FFT at 30MHz, then holding
constant input power and measuring the drop in dBFS as the
frequency is stepped up.
Clearly the overall response shape is doing a good job of
providing approximately 15dB gain from board edge with <-1dB
rolloff to 100MHz. It is important for distortion reasons to stay
away from the rolloff regions of the input step up transformer.
The intended minimum frequency in this application is 100kHz,
well above the 40kHz -1dB measured on t he ADT4-6T while the
maximum intended frequency is 100MHz which is also well
below the measured 180MHz -1dB frequency on the ADT4-6T.
The interstage filter bandlimits the broadband noise out of the
ISL55210 to reduce SNR degradation through the ADC while also
providing a bit of HD2 and HD3 attenuation from the FDA outputs
to the ADC inputs. For instance, a single tone 80MHz at the FDA
output pins will have an HD2 at 160MHz and an HD3 at 240MHz.
The response shape of Figure 11 suggests that HD2 term will get
about 4dB attenuation while the HD3 term will get 13dB
attenuation to the ADC inputs.
CLOCK AND CONTROL OPTIONS
The board offers several optional features that are in some cases
not fully populated. The clock options and two other control
inputs are shown in Figure 13.
The populated path for the ADC clock is the lower right input
through the TC4-19G2 transformer. It is this path that must have
a valid clock input (usually a filtered sine wave) when the
Konverter software is started. Lab tests here were at 10dBm to
14dBm input levels at J4.
An alternate clock path is through an ADI – ADCLK905
differential output ECL clock driver. That path is populated by
adding the SMA at the buffered clock input point at J5, adding
the ECL clock buffer chip, populating the coupling caps (C46 and
C47) and removing the coupling caps from the transformer input
path (C28 and C29). This alternate clock path allows much lower
power sine wave inputs into what is essentially a very low jitter
differential output comparator. Its inputs are also differential, but
one side is biased to the midpoint threshold to run single ended
input. A very low phase noise sine wave inputs as low as -2dBm
will generate the necessary output clock transition times to drive
the ADC clock inputs. The clock chip includes internal 50Ω
termination for the sine wave source.
A similar signal path is shown in Figure 13 just below the
alternate clock path that provides an ADC sync operation if
populated. To use this, add an SMA connector at J7 and the clock
chip at U9. Refer to the ADC data sheet for the operation of this
control path.
The amplifier may also be disabled through a high speed
interface by populating the Pd SMA input through U5, a CMOS
inverter. As delivered, the DC coupled 50Ω termination resistor
holds the input at ground providing a 3.3V output to the disable
control line on the ISL55210. This holds the amplifier in the
enabled mode while connecting the SMA and driving that signal
to a logic high, will disable the amplifier. It is important to
recognize that even in the disable mode a signal path to the ADC
will be present through the feedback resistors. It will be
significantly attenuated from the active mode, but it will not be
an open circuit. The ISL55210 includes two desirable features
when disabled.
1. There are internal back to back diodes across the input
summing junctions to limit the amplitude of high overdrive
signals when disabled (or when active as well). In disable, this
limits the maximum differential voltage available across the
inputs to a diode voltage which is then all that can feed
forward to the ADC – at an attenuated level.
2. A low power monitor circuit holds the output VCM voltage at
the same set point during disable as for the active mode. This
prevents a long turn on time (or AC coupled common mode
voltage spikes) through blocking caps in the output interface
circuit as the amplifier cycles through enable/disable modes
– further protecting the ADC from out of range inputs.
Contact the factory for assistance in exercising these clock and
control options.
FIGURE 11. OVERALL FREQUENCY RESPONSE SHAPE FROM THE
BOARD INPUT TO THE ADC
FIGURE 12. ZOOMED IN RESPONSE SHAPE USING THE ADC TO
MEASURE FLATNESS
-50
-45
-40
-35
-30
-25
-20
-15
-10
1M
1.0M
100M
1G
BOARD #1
BOARD #2
FREQUENCY (Hz)
-16
-15
-14
-13
-12
-11
-10
30
40
50
60
70
80
90
100
110
120
130
FREQUENCY (MHz)
BOARD #1
BOARD #2


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