© 2002 Fairchild Semiconductor Corporation

DS500783

www.fairchildsemi.com

June 2002

Revised June 2002

FIN1025

3.3V LVDS 2-Bit High Speed Differential Driver

General Description

This dual driver is designed for high speed interconnects

utilizing Low Voltage Differential Signaling (LVDS) technol-

ogy. The driver translates LVTTL signal levels to LVDS lev-

els with a typical differential output swing of 350mV which

provides low EMI at ultra low power dissipation even at

high frequencies. This device is ideal for high speed trans-

fer of clock and data.

The FIN1025 can be paired with its companion receiver,

the FIN1026, or any other LVDS receiver.

Features

s Greater than 400Mbs data rate

s Flow-through pinout simplifies PCB layout

s 3.3V power supply operation

s 0.4ns maximum differential pulse skew

s 1.7ns maximum propagation delay

s Low power dissipation

s Power-Off protection

s Meets or exceeds the TIA/EIA-644 LVDS standard

s 14-Lead TSSOP package saves space

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Truth Table

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Don’t Care

Z

= High Impedance

Order Number

Package Number

Package Description

FIN1025MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Name

Description

LVTTL Data Inputs

Non-Inverting Driver Outputs

Inverting Driver Outputs

EN

Driver Enable Pin

EN

Inverting Driver Enable Pin

Power Supply

GND

Ground

NC

No Connect

Inputs

Outputs

EN

EN

HL or OPEN

H

H

L

HL or OPEN

L

L

H

H

L or OPEN

OPEN

L

H

XH

X

Z

Z

L or OPEN

X

X

Z

Z