FIN1531M datasheet(3/6 Pages) FAIRCHILD

Nome de Peças	FIN1531M

Descrição Electrónicos	5V LVDS 4-Bit High Speed Differential Driver

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AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Note 3: All typical values are at TA = 25°C and with VCC = 5V.

Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-

tion.

Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction

(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.

Note 6: fMAX Criteria: Input tR = tF < 1 ns, 0V to 3V, 50% Duty Cycle; Output VOD > 250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.

Note 7: Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

(Note 3)

tPLHD

Differential Propagation Delay

0.5

1.4

2.0

ns

LOW-to-HIGH

tPHLD

Differential Propagation Delay

0.5

1.4

2.0

ns

HIGH-to-LOW

RL = 100 Ω, CL = 10 pF,

tTLHD

Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3 (Note 7)

0.6

0.8

1.2

ns

tTHLD

Differential Output Fall Time (80% to 20%)

0.6

0.8

1.2

ns

tSK(P)

Pulse Skew |tPLH - tPHL|

0.4

ns

tSK(LH),

Channel-to-Channel Skew

0.3

ns

tSK(HL)

(Note 4)

tSK(PP)

Part-to-Part Skew (Note 5)

1.0

ns

fMAX

Maximum Frequency(Note 6)

200

250

ns

tZHD

LVTTL Output Enable Time from Z to HIGH RL = 100Ω, CL = 10 pF,

5.0

ns

tZLD

LVTTL Output Enable Time from Z to LOW

See Figure 4 and Figure 5 (Note 7)

5.0

ns

tHZD

LVTTL Output Disable Time from HIGH to Z

5.0

ns

tLZD

LVTTL Output Disable Time from LOW to Z

5.0

ns

Nº de peça semelhante - FIN1531M

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