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ADRF6806ACPZ-R7 Folha de dados(PDF) 1 Page - Analog Devices

Nome de Peças ADRF6806ACPZ-R7
Descrição Electrónicos  50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO
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Página de início  http://www.analog.com
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50 MHz to 525 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
Data Sheet
ADRF6806
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010–2012 Analog Devices, Inc. All rights reserved.
FEATURES
IQ demodulator with integrated fractional-N PLL
LO frequency range: 50 MHz to 525 MHz
For the following specifications (LPEN = 0)/(LPEN = 1):
Input P1dB: 12.2 dBm/10.6 dBm
Input IP3: 28.5 dBm/25.2 dBm
Noise figure (DSB): 12.2/11.4
Voltage conversion gain: 1 dB/4.2 dB
Quadrature demodulation accuracy
Phase accuracy: <0.5°
Amplitude accuracy: <0.1 dB
Baseband demodulation: 135 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
GENERAL DESCRIPTION
The ADRF6806 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 2.8 GHz to 4.2 GHz. A
programmable quadrature divider (divide ratio = 4 to 80) divides
the output frequency of the VCO down to the required local
oscillator (LO) frequency to drive the mixers in quadrature.
Additionally, an output divider (divide ratio = 4 to 8) generates
a divided-down VCO signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
A reduced power mode of operation is also provided by
programming the serial interface registers to reduce current
consumption, with slightly degraded input linearity and output
current drive.
The ADRF6806 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
MUX
RSET
GND
LON
LOP
MUX
TEMP
SENSOR
GND
DECL3
VCCRF
VCCLO
BUFFER
BUFFER
QBBN
VCCLO
+
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
VCO LDO
2.5V LDO
LE
CLK
SPI
INTERFACE
DATA
MUXOUT
REFIN
ADRF6806
34
GND
LOSEL
35
19
QBBP
18
17
16
DECL1
40
VTUNE
39
DECL2 VCC2
9
10
5
VCC1
2
VCC1
1
8
6
GND 7
14
GND 15
13
12
38
GND 11
37
36
GND
31
IBBN
IBBP
32
33
28
GND
27
RFIN
26
RFIP
25
GND
24
VOCM
23
VCCBB
22
GND
GND
21
20
29
30
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG
MODULUS INTEGER
REG
N COUNTER
GND
4
CPOUT
3
×2
÷2
÷4
DIVIDER
÷2
TO
÷40
VCO
CORE
BUFFER
CTRL
QUAD
÷2
DIV
÷4,
÷6,
÷8
Figure 1.


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