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AD7091BCPZ-RL Folha de dados(PDF) 6 Page - Analog Devices |
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AD7091BCPZ-RL Folha de dados(HTML) 6 Page - Analog Devices |
6 / 20 page AD7091 Data Sheet Rev. A | Page 6 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED PAD TO THE SUBSTRATE, GND. 3 REGCAP 4 GND 1 VDD 2 6 CS 5 CONVST 8 SDO 7 SCLK VIN AD7091 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. The VDD range is from 2.09 V to 5.25 V. Decouple this supply pin to GND. Typical recom- mended capacitor values are 10 µF and 0.1 µF. 2 VIN Analog Input. The single-ended analog input range is from 0 V to VDD. 3 REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Low Dropout (LDO) Regulator. Decouple this output pin separately to GND using a 1 μF capacitor. The voltage at this pin is 1.8 V typical. 4 GND Ground. This pin is the ground reference point for all circuitry on the AD7091. The analog input signal should be referred to this GND voltage. 5 CONVST Conversion Start. Active low, edge triggered logic input. The falling edge of CONVST places the track-and-hold into hold mode and initiates a conversion. 6 CS Chip Select. Active low logic input. The serial bus is enabled when CS is held low; in this mode CS is used to frame the output data on the SPI bus. 7 SCLK Serial Clock. This pin acts as the serial clock input. 8 SDO Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data is provided MSB first. 9 EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and for maximum thermal capability, solder the exposed pad to the substrate, GND. |
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