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R1Q6A7236AB Folha de dados(PDF) 9 Page - Renesas Technology Corp |
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R1Q6A7236AB Folha de dados(HTML) 9 Page - Renesas Technology Corp |
9 / 39 page R1QAA72 / R1QDA72 Series Rev. 0.11 : 2013.01.15 PAGE:9 hinS=11111.1111.1111.1111.1111--- 11111.1111.1111.1111.1111---00000.0000.0000.0000.0000--- 72M_36M Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation V DD SET-UP Cycle V DDQ V REF /DOFF 2. Double clock mode K, /K Fix High (=Vddq) C, /C Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation V DD SET-UP Cycle V DDQ V REF /DOFF 1. Single clock mode (C and /C pins fixed High) K, /K Fix High (=Vddq) General Description Power-up and Initialization Sequence -V DD must be stable before K, /K clocks are applied. - Recommended voltage application sequence : V SS V DD V DDQ & VREF V IN. (0 V to VDD, VDDQ < 200 ms) - Apply V REF after VDDQ or at the same time as VDDQ. - Then execute either one of the following three sequences. 1. Single Clock Mode (C and /C tied high) - Drive /DOFF high (/DOFF can be tied high from the start). - Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). 2. Double Clock Mode (C and /C control outputs) (II series only) - Drive /DOFF high (/DOFF can be tied high from the start) - Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series). This meets the QDR common specification of 20 us. When the operating frequency is less than 180 MHz, 2048 cycles are required (II series). 3. DLL/PLL Off Mode (/DOFF tied low) - In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series). These meet the QDR common specification of 20 us. R10DS0169EJ0011 |
Nº de peça semelhante - R1Q6A7236AB |
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Descrição semelhante - R1Q6A7236AB |
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