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R1Q6A7236AB Folha de dados(PDF) 31 Page - Renesas Technology Corp

Nome de Peças R1Q6A7236AB
Descrição Electrónicos  72-Mbit QDR II SRAM 4-word Burst
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
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R1QAA72 / R1QDA72 Series
Rev. 0.11 : 2013.01.15
PAGE:31
TAP Controller Instruction Set
IR2 IR1 IR0 Instruction
Description
Notes
0
0
0 EXTEST
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register cells
at output balls are used to apply test vectors, while those at
input balls capture test results. Typically, the first test vector to
be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output driver is
turned on and the PRELOAD data is driven onto the output balls.
1, 2, 3, 5
0
0
1 IDCODE
The IDCODE instruction causes the ID ROM to be loaded into
the ID register when the controller is in capture-DR mode and
places the ID register between the TDI and TDO balls in shift-
DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in
the Test-Logic-Reset state.
0
1
0 SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register,
all RAM outputs are forced to an inactive drive state (high-Z),
moving the TAP controller into the capture-DR state loads the
data in the RAMs input into the boundary scan register, and the
boundary scan register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
3, 4, 5
0
1
1 RESERVED
The RESERVED instructions are not implemented but are
reserved for future use. Do not use these instructions.
10
0
SAMPLE
(/PRELOAD)
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR state
loads the data in the RAMs input and I/O buffers into the
boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the TAP
to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although
allowing the TAP to SAMPLE metastable input will not harm the
device, repeatable results cannot be expected. Moving the
controller to shift-DR state then places the boundary scan
register between the TDI and TDO balls.
3, 5
1
0
1 RESERVED
-
1
1
0 RESERVED
-
1
1
1 BYPASS
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the shift-DR state.
This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
Notes:
1.
Data in output register is not guaranteed if EXTEST instruction is loaded.
2.
After performing EXTEST, power-up conditions are required in order to return part to normal
operation.
3.
RAM input signals must be stabilized for long enough to meet the TAPs input data capture
setup plus hold time (t
CS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
4.
Clock recovery initialization cycles are required after boundary scan.
5.
For R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, ODT is disabled in EXTEST,
SAMPLE-Z or SAMPLE mode.
Common
R10DS0169EJ0011


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