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R1QGA3618CB Folha de dados(PDF) 24 Page - Renesas Technology Corp

Nome de Peças R1QGA3618CB
Descrição Electrónicos  36-Mbit DDRII SRAM 2-word Burst
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1QGA3618CB Folha de dados(HTML) 24 Page - Renesas Technology Corp

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PAGE : 24
Rev. 0.09a : 2011.09.14
R1QBA36**CB* / R1QEA36**CB* Series
hinS=00000.0111.0111.0000.0000---
00000.0111.0111.0000.0000---
00000.0000.0000.0000.0000---RL=2.5
Notes:
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and
hold times for all latching clock edges.
2. V
DD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock
time begins once V
DD , VDDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
This specification meets the QDR common spec. of 20 us.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured 100 mV from steady-state voltage.
6. At any given voltage and temperature t
CHQZ is less than tCHQX1 and tCHQV.
7. These parameters are sampled.
8. t
AVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number (Marking
Name). The following is the spec for the actual frequency.
0.30 ns for 533MHz & >500MHz
0.33 ns for 500MHz & >450MHz
0.40 ns for 450MHz & 250MHz
9. t
DVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The
following is the spec for the actual frequency.
0.20 ns for 533MHz & >500MHz
0.22 ns for 500MHz & >450MHz
0.25 ns for 450MHz & >400MHz
0.28 ns for 400MHz & 250MHz
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
2. Control input signals may not be operated with pulse widths less than t
KHKL (min).
3. V
DDQ is +1.5 V DC. VREF is +0.75 V DC.
4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
K, /K rising edge
to data-in hold
K rising edge
to control inputs
hold
K rising edge
to address hold
Hold Times
Data-in valid to
K, /K rising edge
Control inputs
valid to
K rising edge
Address valid to
K rising edge
Setup Times
Parameter
t
KHDX
t
KHIX
(QDRII+ B4 & DDRII+)
t
KHIX
(QDRII+ B2)
t
KHAX
(QDRII+ B4 & DDRII+)
t
KHAX
(QDRII+ B2)
t
DVKH
t
IVKH
(QDRII+ B4 & DDRII+)
t
IVKH
(QDRII+ B2)
t
AVKH
(QDRII+ B4 & DDRII+)
t
AVKH
(QDRII+ B2)
Symbol
0.20
0.30
0.30
0.20
0.30
0.30
Min
-19
Max
0.22
0.33
0.33
0.22
0.33
0.33
Min
-20
Max
0.25
0.40
0.40
0.25
0.40
0.40
Min
-22
Max
0.28
0.40
0.40
0.28
0.40
0.40
Min
-25
Max
0.28
0.40
0.40
0.28
0.40
0.40
Min
-27
Max
0.28
0.40
0.40
0.28
0.40
0.40
Min
-30
Max
ns
ns
ns
ns
ns
ns
Unit
1, 9
1, 8
1, 8
1, 9
1, 8
1, 8
Notes
R10DS0159EJ0009


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