R1QBA72 / R1QEA72 Series

Rev. 0.11 : 2013.01.15

PAGE:26

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with

normal operation of the device, TCK must be tied to V

TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up

resistor.

TDO should be left unconnected.

Test Access Port (TAP) Pins

Symbol I/O Pin assignments Description

Notes

TCK

2R

Test clock input. All inputs are captured on the rising edge of

TCK and all outputs propagate from the falling edge of TCK.

TMS

10R

Test mode select. This is the command input for the TAP

controller state machine.

TDI

11R

Test data input. This is the input side of the serial registers

placed between TDI and TDO. The register placed between

TDI and TDO is determined by the state of the TAP controller

state machine and the instruction that is currently loaded in

the TAP instruction.

TDO

1R

Test data output. Output changes in response to the falling

edge of TCK. This is the output side of the serial registers

placed between TDI and TDO.

Notes:

The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while

TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM

POWER-UP.

Common

R10DS0170EJ0011