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R1QDA7236AB Folha de dados(PDF) 17 Page - Renesas Technology Corp |
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R1QDA7236AB Folha de dados(HTML) 17 Page - Renesas Technology Corp |
17 / 39 page R1QBA72 / R1QEA72 Series Rev. 0.11 : 2013.01.15 PAGE:17 Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Input voltage on any ball V IN −0.5 to V DD + 0.5 (2.5 V max.) V1, 4 Input/output voltage V I/O −0.5 to V DDQ + 0.5 (2.5 V max.) V1, 4 Core supply voltage V DD −0.5 to 2.5 V 1, 4 Output supply voltage V DDQ −0.5 to V DD V1, 4 Junction temperature Tj +125 (max) °C5 Storage temperature T STG −55 to +125 °C Notes: 1. All voltage is referenced to V SS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: V SS, VDD, VDDQ, VREF then V IN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of V DDQ. 5. Some method of cooling or airflow should be considered in the system. (Especially for high frequency or ODT parts) Common Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Power supply voltage -- core V DD 1.7 1.8 1.9 V 1 Power supply voltage -- I/O V DDQ 1.4 1.5 V DD V1, 2 Input reference voltage -- I/O V REF 0.68 0.75 0.95 V 3 Input high voltage V IH (DC) V REF + 0.1 ⎯ V DDQ + 0.3 V 1, 4, 5 Input low voltage V IL (DC) −0.3 ⎯ V REF − 0.1 V 1, 4, 5 Notes: 1. At power-up, V DD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or V DDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ. During normal operation, V DDQ must not exceed VDD. 2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings table due to current from V DDQ. 3. Peak to peak AC component superimposed on V REF may not exceed 5% of VREF. 4. These are DC test criteria. The AC V IH / VIL levels are defined separately to measure timing parameters. 5. Overshoot: V IH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: V IL (AC) ≥−0.5 V for t ≤ tKHKH/2 During normal operation, V IH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. R10DS0170EJ0011 |
Nº de peça semelhante - R1QDA7236AB |
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Descrição semelhante - R1QDA7236AB |
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