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R5F64207LFB Folha de dados(PDF) 69 Page - Renesas Technology Corp |
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R5F64207LFB Folha de dados(HTML) 69 Page - Renesas Technology Corp |
69 / 103 page R01DS0069EJ0120 Rev.1.20 Page 69 of 97 Jan 27, 2012 R32C/120 Group 5. Electrical Characteristics Notes: 1. This value is the deviation from target frequency. 2. This value is applicable only when the main clock oscillation is stable. 3. This value is the time until the PLF1 bit in the PLS register becomes 1. Table 5.11 Electrical Characteristics of Voltage Regulator for Internal Logic (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement Condition Value Unit Min. Typ. Max. VVDC1 Output voltage 1.5 V Table 5.12 Electrical Characteristics of Low Voltage Detector (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement Condition Value Unit Min. Typ. Max. ΔVdet Detected voltage error ±0.2 V Vdet(R)-Vdet(F) Hysteresis width 0 V — Self-consuming current VCC = 5.0 V, low voltage detector enabled 4µA td(E-A) Operation start time of low voltage detector 150 µs Table 5.13 Electrical Characteristics of Oscillator (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement Condition Value Unit Min. Typ. Max. fSO(PLL) PLL clock self-oscillation frequency 35 50 80 MHz | ΔfLOCK| Lock detection (1) 2% | ΔfUNLOCK| Unlock detection (1) 2% tLOCK(PLL) PLL lock time (2, 3) f(XRef) =4MHz 1ms tjitter(p-p) PLL jitter period (p-p) 2.0 ns f(OCO) On-chip oscillator frequency 94 125 156 kHz |
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Descrição semelhante - R5F64207LFB |
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