Circuit Note

CN-0121

Circuit Designs Using Analog Devices Products

Apply these product pairings quickly and with confidence.

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Devices Connected/Referenced

AD9910

1 GSPS Direct Digital Synthesizer (DDS)

AD9520

Clock Generator and Distribution IC

ADCLK846

High Speed LVDS Clock Fanout Buffer

Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers

Rev. A

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CIRCUIT FUNCTION AND BENEFITS

Synchronization of multiple DDS devices allows precise digital

tuning control of the phase and amplitude across multiple

frequency carriers. This type of control is useful in radar

applications and quadrature (I/Q) upconversion for side-band

suppression.

The circuit in Figure 1 demonstrates how to synchronize four

AD9910 1 GSPS, DDS chips using the AD9520 clock generator

and the ADCLK846 clock fanout buffer. The result is precise

phase alignment between the clock and output signals of four

AD9910 devices.

AD9910

(MASTER)

+ SYNC_IN

– SYNC_IN

– SYNC_OUT

SYNC_CLK

AOUT

CLK1

CLK1

CLOCK

CMOS

LEVELS

CMOS

LEVEL

PECL

LEVELS

REF CLK

IO_UPDATE

AD9910

(SLAVE)

REF CLK

+ SYNC_IN

– SYNC_IN

+ SYNC_IN

– SYNC_IN

+ SYNC_IN

– SYNC_IN

SYNC_CLK

AOUT

IO_UPDATE

AD9910

(SLAVE)

REF CLK

SYNC_CLK

AOUT

IO_UPDATE

AD9910

(SLAVE)

REF CLK

SYNC_CLK

AOUT

IO_UPDATE

+ SYNC_OUT

CH1

CH2

CH3

CH4

DG2020A

DATA

GENERATOR

AD9520

Q0

Q1

Q2

Q3

Q4

ADCLK846

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

LVDS

LEVELS

LVDS

LEVELS

Figure 1. Setup for Synchronization of Multiple AD9910’s (Simplified Schematic: Decoupling, Power, and All Connections Not Shown)