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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ML4805CS Folha de dados(PDF) 10 Page - Fairchild Semiconductor |
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ML4805CS Folha de dados(HTML) 10 Page - Fairchild Semiconductor |
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10 / 13 page  ML4805 10 REV. 1.1 3/9/2001 Generating VCC The ML4805 is a voltage-fed part. It requires an external 15V ±10% or better Zener shunt voltage regulator, or some other controlled supply, to regulate the voltage supplied to the part at 15V nominal. This allows a low power dissipation while at the same time delivering 13V nominal of gate drive at the PWM OUT and PFC OUT outputs. If using a Zener diode, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the ML4805 itself (8.5mA max.) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC limit of 16.5V (max) and driving a total gate charge of 110nC at 100kHz (1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is: The ML4805 should be locally bypassed with a 10nF and a 1 µF ceramic capacitor. In most applications, an electrolytic capacitor of between 100 µF and 330µF is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 3 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 4 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. FUNCTIONAL DESCRIPTION (Continued) Figure 4. Leading/Trailing Edge Control Scheme Figure 3. Typical Trailing Edge Control Scheme RAMP VEAO TIME VSW1 TIME REF EA – + – + OSC DFF R D Q Q CLK U1 RAMP CLK U4 U3 C1 RL I4 SW2 SW1 + DC I1 I2 I3 VIN L1 U2 REF EA – + – + OSC DFF R D Q Q CLK U1 RAMP CLK U4 U3 C1 RL I4 SW2 SW1 + DC I1 I2 I3 VIN L1 VEAO CMP U2 RAMP VEAO TIME VSW1 TIME IkHz nC mA GATEDRIVE =´ = 100 110 11 R VV mA mA BIAS = - + = 20 165 75 11 180 . . Ω |
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Descrição semelhante - ML4805CS |
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