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ML4821CS Folha de dados(PDF) 8 Page - Fairchild Semiconductor

Nome de Peças ML4821CS
Descrição Electrónicos  Power Factor Controller
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

ML4821CS Folha de dados(HTML) 8 Page - Fairchild Semiconductor

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ML4821
PRODUCT SPECIFICATION
8
REV. 1.0.2 6/19/01
Under Voltage Lockout, OVP and Current Limit
On power-up the ML4821 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when VCC reaches 16V. When VCC drops below
9V, the UVLO condition is imposed. During the UVLO
condition, the VREF pin is “off”, making it usable as a “flag”
for starting up a down-stream PWM converter.
OVP, Shutdown, and IC Bias
When the input to the OVP comparator exceeds VREF, the
output of the ML4821 is inhibited. The OVP input also
functions as a “sleep” input, putting the IC into the low
quiescent UVLO state when the OVP pin is pulled below
0.7V.
Figure 7. Gain Modulator Linearity.
Figure 8. Under-Voltage Lockout Block Diagram.
500
0
0
100
300
400
500
SINE INPUT CURRENT (
µA)
200
100
200
300
400
1.0
1.5
2.5
3.5
4.5
5.5
RT = 5k
VRMS = 3V
ENABLE
VREF
+
+
15
16
INTERNAL
BIAS
4.4V
LOGIC
POWER
VREF
9V
VCC
Figure 9. Total Supply Current vs. Supply Voltage.
Figure 10. Reference Load Regulation.
40
10
0
010
20
30
VCC SUPPLY VOLTAGE (V)
TA = 25
°C
20
30
VCC = 15V
TA = –55
°C
TA = 25
°C
TA = 125
°C
0
–4.0
–8.0
–12
–16
–20
–24
0
20
40
60
80
100
120
IREF, REFERENCE SOURCE CURRENT (mA)


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