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AD5425YRM-REEL7 Folha de dados(PDF) 6 Page - Analog Devices |
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AD5425YRM-REEL7 Folha de dados(HTML) 6 Page - Analog Devices |
6 / 25 page Data Sheet AD5425 Rev. C | Page 5 of 24 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD =2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 V DD = 2.5 V to 5.5 V Unit Conditions/Comments f SCLK 50 MHz max Maximum clock frequency t 1 20 ns min SCLK cycle time t 2 8 ns min SCLK high time t 3 8 ns min SCLK low time t 4 2 13 ns min SYNC falling edge to SCLK falling edge setup time t 5 5 ns min Data setup time t 6 3 ns min Data hold time t 7 5 ns min SYNC rising edge to SCLK falling edge t 8 30 ns min Minimum SYNC high time t 9 0 ns min SCLK falling edge to LDAC falling edge t 10 12 ns min LDAC pulse width t 11 10 ns min SCLK falling edge to LDAC rising edge 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by control bits of serial word. Figure 2. Timing Diagram t8 SCLK SYNC DIN LDAC2 LDAC1 DB7 t4 DB0 NOTES: 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. t11 t10 t1 t9 t5 t6 t2 t3 t7 |
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Descrição semelhante - AD5425YRM-REEL7 |
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