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AD5546 Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças AD5546
Descrição Electrónicos  Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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AD5405
Rev. B | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Limit at TMIN, TMAX
Unit
Conditions/Comments
Write Mode
t1
0
ns min
R/W-to-CS setup time
t2
0
ns min
R/W-to-CS hold time
t3
10
ns min
CS low time
t4
10
ns min
Address setup time
t5
0
ns min
Address hold time
t6
6
ns min
Data setup time
t7
0
ns min
Data hold time
t8
5
ns min
R/W high to CS low
t9
7
ns min
CS min high time
t14
10
ns typ
CS rising-to-LDAC falling time
t15
12
ns typ
LDAC pulse width
t16
10
ns typ
CS rising-to-LDAC rising time
t17
10
ns typ
LDAC falling-to-CS rising time
Data Readback Mode
t10
0
ns typ
Address setup time
t11
0
ns typ
Address hold time
t12
5
ns typ
Data access time
35
ns max
t13
5
ns typ
Bus relinquish time
10
ns max
Update Rate
21.3
MSPS
Consists of CS min high time, CS low time, and output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
t7
DATA VALID
t6
t2
CS
R/W
DATA
t1
t
2
t13
t12
t3
t
8
t9
DACA/DACB
t4
t5
t11
t10
LDAC2
LDAC1
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t16
t14
t15
t17
DATA VALID
Figure 2. Timing Diagram
IOL
200
μA
IOH
200
μA
CL
50pF
TO
OUTPUT
PIN
VOH (MIN) + VOL (MAX)
2
Figure 3. Load Circuit for Data Timing Specifications


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