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AD9914 Folha de dados(PDF) 5 Page - Analog Devices |
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AD9914 Folha de dados(HTML) 5 Page - Analog Devices |
5 / 48 page Data Sheet AD9914 Rev. C | Page 5 of 48 AC SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments REF CLK INPUT Input frequency range REF CLK Multiplier Bypassed Input Frequency Range 500 3500 MHz Maximum fOUT is 0.4 × fSYSCLK Duty Cycle 45 55 % Minimum Differential Input Level 632 mV p-p Equivalent to 316 mV swing on each leg System Clock (SYSCLK) PLL Enabled VCO Frequency Range 2400 2500 MHz VCO Gain (KV) 60 MHz/V Maximum PFD Rate 125 MHz CLOCK DRIVERS SYNC_CLK Output Driver Frequency Range 146 MHz Duty Cycle 45 50 55 % Rise Time/Fall Time (20% to 80%) 650 ps SYNC_OUT Output Driver 10 pF load Frequency Range 9.1 MHz Duty Cycle 33 66 % CFR2 register, Bit 9 = 1 Rise Time (20% to 80%) 1350 ps 10 pF load Fall Time (20% to 80%) 1670 ps 10 pF load DAC OUTPUT CHARACTERISTICS Output Frequency Range (1st Nyquist Zone) 0 1750 MHz Output Resistance 50 Ω Single-ended (each pin internally terminated to AVDD (3.3V)) Output Capacitance 1 pF Full-Scale Output Current 20.48 mA Range depends on DAC RSET resistor Gain Error −10 +10 % FS Output Offset 0.6 μA Voltage Compliance Range AVDD − 0.50 AVDD + 0.50 V Wideband SFDR See the Typical Performance Characteristics section 101.1 MHz Output −66 dBc 0 MHz to 1750 MHz 427.5 MHz Output −65 dBc 0 MHz to 1750 MHz 696.5 MHz Output −57 dBc 0 MHz to 1750 MHz 1396.5 MHz Output −52 dBc 0 MHz to 1750 MHz Narrow-Band SFDR See the Typical Performance Characteristics section 100.5 MHz Output −95 dBc ±500 kHz 427.5 MHz Output −95 dBc ±500 kHz 696.5 MHz Output −95 dBc ±500 kHz 1396.5 MHz Output −92 dBc ±500 kHz DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down 45 ns Power-down mode loses DAC/PLL calibration settings Time Required to Leave Power-Down 250 ns Must recalibrate DAC/PLL Minimum Master Reset time 24 SYSCLK cycles Maximum DAC Calibration Time (tCAL) 152 µs fCAL = fSYSCLK/384 USR0 register, Bit 6 = 0; see the DAC Calibration Output section for formula Maximum PLL Calibration Time (tREF_CLK) 16 ms PFD rate = 25 MHz 8 ms PFD rate = 50 MHz Maximum Profile Toggle Rate 2 SYNC_CLK period |
Nº de peça semelhante - AD9914 |
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Descrição semelhante - AD9914 |
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