BelaSigna 200

2.5 Input Stage

• Two separate input channels, each with two multiplexed inputs

• Two configurable preamplifiers for improved input dynamic range matching

• Two analog third-order anti-aliasing filters

• Two 16-bit oversampling ΣΔ A/D converters

• Two ninth-order low-delay wave digital filters (WDFs) for decimation and DC removal with configurable digital gains for optimal

channel matching

2.6 Output Stage

• Two output channels (full stereo)

• Two 16-bit oversampling ΣΔ D/A converters

• Two line-level analog outputs

• Two configurable output attenuators for improved output dynamic range matching

• Two analog third-order anti-aliasing filters

• Two pulse-density modulation (PDM)-based direct digital outputs capable of driving low-impedance loads

2.7 Peripherals and Interfaces

2.7.1. Analog Interfaces

• Six external low-speed A/D converter (LSAD) inputs can be used with analog trimmers (e.g., potentiometers, analog switches, etc.)

• Two internal LSAD inputs tied directly to ground and supply can be used for supply monitoring

2.7.2. Digital Interfaces

• 16-pin general-purpose I/O (GPIO) interface

• Serial peripheral interface (SPI) communications port with interface speeds up to 640kbps at 1.28MHz system clock

• Pulse-code modulation (PCM) interface for high-bandwidth digital audio I/O

• Configurable RS-232 universal asynchronous receiver/transmitter (UART)

• RS-232-based communications port for debugging and in-circuit emulation

• Two-wire synchronous serial (TWSS) interface with speeds up to 100kbps at 1.28MHz system clock and up to 400kbps at higher

system clocks (slave mode support only)

2.7.3. System

• Integrated watchdog timer

• General-purpose timer

• External clock input division circuitry to support a wide range of external clock speeds

Rev. 16 | Page 3 of 43 | www.onsemi.com