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ADMCF328BR Folha de dados(PDF) 11 Page - Analog Devices |
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ADMCF328BR Folha de dados(HTML) 11 Page - Analog Devices |
11 / 36 page ADMCF328 –11– REV. A VRST VDD RESET VRST – VHYST tRST Figure 5. Power-On Reset Operation The ADMCF328 reset sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the MSTAT register and performs a full reset of all of the motor control periph- erals. Following a power-up, it is possible to initiate a DSP core and motor control peripheral reset by pulling the RESET pin low. The RESET signal must meet the minimum pulse- width specification, tRSP. Following the reset sequence, the DSP core starts executing code from the internal PM ROM located at 0x0800. DSP Control Registers The DSP core has a system control register, SYSCNTL, memory mapped at DM (0x3FFF). SPORT1 is configured as a serial port when Bit 10 is set, or as flags and interrupt lines when this bit is cleared. For proper operation of the ADMCF328, all other bits in this register must be cleared. The DSP core has a wait state control register, MEMWAIT, memory mapped at DM (0x3FFE). The default value of this resister is 0xFFFF. For proper operation of the ADMCF328, this register must always contain the value 0x8000. The configuration of both the SYSCNTL and MEMWAIT reg- isters of the ADMCF328 are shown at the end of the data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMCF328 is a flexible, programmable, three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction motors (ACIM) or permanent magnet synchronous motors (PMSM). In addition, the PWM block contains special functions that considerably simplify the generation of the required PWM switching patterns for control of electronically commutated motors (ECM) or brushless dc motors (BDCM). The PWM generator produces three pairs of active high PWM signals on the six PWM output pins (AH, AL, BH, BL, CH, and CL). The six PWM output signals consist of three high side drive signals (AH, BH, and CH) and three low side drive signals (AL, BL, and CL). The switching frequency, dead time, and minimum pulsewidths of the generated PWM patterns are programmable using, respectively, the PWMTM, PWMDT, and PWMPD registers. In addition, three registers (PWMCHA, PWMCHB, and PWMCHC) control the duty cycles of the three pairs of PWM signals. Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMSEG register. In addition, three control bits of the PWMSEG register permit crossover of the two signals of a PWM pair for easy control of ECM or BDCM. In crossover mode, the PWM signal destined for the high side switch is diverted to the complementary low side output, and the signal destined for the low side switch is diverted to the corresponding high side output signal. In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. In general, there are two common isolation techniques: optical isolation using optocouplers, and transformer isolation using pulse transformers. The PWM controller of the ADMCF328 permits mixing of the output PWM signals with a high frequency chopping signal to permit an easy interface to such pulse trans- formers. The features of this gate-drive chopping mode can be controlled by the PWMGATE register. There is an 8-bit value within the PWMGATE register that directly controls the chopping frequency. In addition, high frequency chopping can be indepen- dently enabled for the high side and the low side outputs using separate control bits in the PWMGATE register. The PWM generator is capable of operating in two distinct modes: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period, so that the resultant PWM patterns are symmetri- cal about the midpoint of the PWM period. In the double update mode, a second updating of the PWM duty cycle values is imple- mented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. This technique also permits the closed-loop controller to change the average voltage applied to the machine winding at a faster rate, allowing wider closed-loop bandwidths to be achieved. The operat- ing mode of the PWM block (single or double update mode) is selected by a control bit in MODECTRL register. The PWM generator of the ADMCF328 also provides an internal signal that synchronizes the PWM switching frequency to the A/D operation. In single update mode, a PWMSYNC pulse is produced at the start of each PWM period. In double update mode, an additional PWMSYNC pulse is produced at the mid- point of each PWM period. The width of the PWMSYNC pulse is programmable through the PWMSYNCWT register. The PWM signals produced by the ADMCF328 can be shut off in a number of different ways. First, there is a dedicated asynchronous PWM shutdown pin, PWMTRIP, which, when brought LO, instantaneously places all six PWM outputs in the OFF state. In addition, PWM shutdown is initiated when the voltage on the analog input pin (ISENSE) is pulled below the trip voltage level, corresponding to an over-current fault. Because these two hardware shutdown mechanisms are asynchronous, and the associated PWM disable circuitry does not use clocked logic, the PWM will shut down even if the DSP clock is not run- ning. The PWM system may also be shut down from software by writing to the PWMSWT register. Status information about the PWM system of the ADMCF328 is available to the user in the SYSSTAT register. In particular, the state of PWMTRIP is available, as well as a status bit that indicates whether operation is in the first half or the second half of the PWM period. |
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