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Datasheet

Datasheet

BU21029MUV

TSZ02201-0Y1Y0F300110-1-2

© 2011 ROHM Co., Ltd. All rights reserved.

11.Nov.2013 Rev.004

www.rohm.co.jp

TSZ22111・15・001

●WRITE CYCLE

The host first sends an address byte to the BU21029MUV controller. This address byte is composed of the 7-bit slave byte

on the upper seven bits and the Read/Write bit on the LSB. If the controller receives a valid address byte, it issues an

acknowledgement. The host processor can transmit a command only after receiving the acknowledgement for the address

byte from the controller. The controller then sends back another acknowledgement, allowing the host to continually send

write data or issue a STOP command.

S：START condition

P：STOP condition

A：ACK

N：NACK

Figure 1. Write Protocol

●READ CYCLE

The READ bit is the LSB of the address byte. When read mode is selected, BU21029MUV sends back the data byte

followed by an acknowledgement to the host. The data sent back is either the conversion result or the register value,

depending on the last command byte received by BU21029MUV. The host needs to resend the conversion command with

setting "CMSK=1" if it has read the register value before reading the conversion result. BU21029MUV sends the next data

byte after it has received an acknowledgement from the host for the previous data byte. Upon receiving the last data byte,

the host finishes read access by issuing a START (or STOP) commands followed by NACK (not acknowledged) command.

S：START condition

P：STOP condition

A：ACK

N：NACK

Figure 2. Read Protocol

●SCL STRETCH

If the host reads the conversion result while conversion is ongoing, BU21029MUV notifies it through the SCL_STRETCH

function. (*1) SCL_STRECH is released when conversion function is finished.

Figure 3. SCL Stretch Timing