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LM1973 Folha de dados(PDF) 4 Page - Texas Instruments

Nome de Peças LM1973
Descrição Electrónicos  LM1973 關Pot 3-Channel 76dB Audio Attenuator with Mute
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LM1973
SNAS093B – DECEMBER 1994 – REVISED MARCH 2013
www.ti.com
TEST CIRCUIT DIAGRAMS
Figure 3. Timing Diagram
PIN DESCRIPTIONS
Signal Ground (1, 5, 17): Each input has its own independent ground, GND1, GND2, and GND3.
Signal Input (2, 4, 18): There are 3 independent signal inputs, IN1, IN2, and IN3.
Signal Output (6, 16, 20): There are 3 independent signal outputs, OUT1, OUT2, and OUT3.
Voltage Supply (13, 15):
Voltage Supply (7, 19): Negative voltage supply pins, VSS1 and VSS2. To be tied to ground in a single supply
configuration.
AC Ground (3, 14): These two pins are not physically connected to the die in any way (i.e., No bondwires).
These pins must be AC grounded to prevent signal coupling between any of the pins nearby. Pin 14
should be connected to pins 13 and 15 for ease of wiring and the best isolation.
Logic Ground (8): Digital signal ground for the interface lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.
Clock (9): The clock input accepts a TTL or CMOS level signal. The clock input is used to load data into the
internal shift register on the rising edge of the input clock waveform.
Load/Shift (10): The load/shift input accepts a TTL or CMOS level signal. This is the enable pin of the device,
allowing data to be clocked in while this input is low (0V).
Data-In (11): The data-in input accepts a TTL or CMOS level signal. This pin is used to accept serial data from a
microcontroller that will be latched and decoded to change a channel's attenuation level.
Data-Out (12): This pin is used in daisy-chain mode where more than one
μPot is controlled via the same data
line. As the data is clocked into the chain from the
μC, the preceding data in the shift register is shifted out
the DATA-OUT pin to the next
μPot in the chain or to ground if it is the last μPot in the chain. The
LOAD/SHIFT line goes high once all of the new data has been shifted into each of its respective registers.
4
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