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ST9435GP Folha de dados(PDF) 1 Page - Stanson Technology |
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ST9435GP Folha de dados(HTML) 1 Page - Stanson Technology |
1 / 6 page ST9435GP P Channel Enhancement Mode MOSFET -15.0A STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com Copyright © 2009, Stanson Corp. ST9435GP 2010. V1 DESCRIPTION ST9435GP is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These device is particularly suited for low voltage application, notebook computer power management and other battery circuits where high-side switching. PIN CONFIGURATION ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symb ol Typical Unit Drain-Source Voltage VDSS -30 V Gate-Source Voltage VGSS ±20 V Continuous Drain Current (TJ=150℃) TA=25℃ TA=100℃ ID -15.0 -8.0 A Pulsed Drain Current IDM -60 A Power Dissipation TA=25℃ PD 62.5 W Operation Junction Temperature TJ -55/150 ℃ Storgae Temperature Range TSTG -55/150 ℃ Thermal Resistance-Junction to Ambient RθJA 62 ℃/W FEATURE -30V/-10A, RDS(ON) = 50m @VGS = -10V -30V/-5A, RDS(ON) = 80m @VGS = -4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability TO-220 package design |
Nº de peça semelhante - ST9435GP |
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Descrição semelhante - ST9435GP |
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