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ML4824 Folha de dados(PDF) 10 Page - Fairchild Semiconductor

Nome de Peças ML4824
Descrição Electrónicos  Power Factor Correction and PWM Controller Combo
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

ML4824 Folha de dados(HTML) 10 Page - Fairchild Semiconductor

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ML4824
PRODUCT SPECIFICATION
10
REV. 1.0.6 11/7/03
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on VFB is less than
its nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2 is
generally used as the sampling point for a voltage represent-
ing the current in the primary of the PWM’s output trans-
former, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a
ramp voltage generated by a second set of timing compo-
nents (RRAMP2, CRAMP2), which will have a minimum
value of zero volts and should have a peak value of approxi-
mately 5V. In voltage mode operation, feedforward from the
PFC output buss is an excellent way to derive the timing
ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation::
where CSS is the required soft start capacitance, and tDELAY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
Solving for the minimum value of CSS:
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the SS
capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the VIN OK comparator at
start-up. The magnitude of VFB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a
1.0
µF soft start capacitor will allow time for VFB and PFC
out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.
GENERATING VCC
The ML4824 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power dissipa-
tion while at the same time delivering 10V of gate drive at
the PWM OUT and PFC OUT outputs. It is important to
limit the current through the part to avoid overheating or
destroying it. This can be easily done with a single resistor in
series with the Vcc pin, returned to a bias supply of typically
18V to 20V. The resistor’s value must be chosen to meet the
operating current requirement of the ML4824 itself (19mA
max) plus the current required by the two gate driver outputs.
EXAMPLE:
With a VBIAS of 20V, a VCC limit of 14.6V (max) and the
ML4824 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the
gate driver current required is:
To check the maximum dissipation in the ML4824, find the
current at the minimum VCC (12.4V)::
The maximum allowable ICC is 55mA, so this is an accept-
able design.
The ML4824 should be locally bypassed with a 10nF and a
1
µF ceramic capacitor. In most applications, an electrolytic
capacitor of between 100
µF and 330µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
Figure 3. External Component Connections to VCC
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme.
C
SS
t
DELAY
50
µA
1.25V
----------------
×
=
(6)
C
SS
5ms
50
µA
1.25V
----------------
×
200nF
==
I
GATEDRIVE
100kHz
100nC
×
11mA
==
(7)
R
BIAS
20V
14.6V
19mA
11mA
+
---------------------------------------
180
==
(8)
I
CC
20V
12.4V
180
---------------------------------
42.2mA
==
(9)
ML4824
VCC
GND
VBIAS
10nF
CERAMIC
1
µF
CERAMIC
RBIAS


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