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AD2S83 Folha de dados(PDF) 9 Page - Analog Devices |
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AD2S83 Folha de dados(HTML) 9 Page - Analog Devices |
9 / 19 page AD2S83 –9– REV. E 8. Offset Adjust Offsets and bias currents at the integrator input can cause an additional positional offset at the output of the converter of 1 arc minute typical, 5.3 arc minutes maximum. If this can be tolerated, then R8 and R9 can be omitted from the circuit. If fitted, the following values of R8 and R9 should be used: R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer To adjust the zero offset, ensure the resolver is disconnected and all the external components are fitted. Connect the COS pin to the REFERENCE INPUT and the SIN pin to the SIGNAL GROUND and with the power and reference applied, adjust the potentiometer to give all “0s” on the digital output bits. The potentiometer may be replaced with select on test resistors if preferred. DATA TRANSFER To transfer data the INHIBIT input should be used. The data will be valid 490 ns after the application of a logic “LO” to the INHIBIT. This is regardless of the time when the INHIBIT is applied and allows time for an active BUSY to clear. By using the ENABLE input the two bytes of data can be transferred after which the INHIBIT should be returned to a logic “HI” state to enable the output latches to be updated. BUSY Output The validity of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL level. A BUSY pulse is initiated each time the input moves by the analog equivalent of one LSB and the internal counter is incremented or decremented. INHIBIT Input The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a BUSY pulse to refresh the output data. ENABLE Input The ENABLE input determines the state of the output data. A logic “HI” maintains the output data pins in the high imped- ance condition, and the application of a logic “LO” presents the data in the latches to the output pins. The operation of the ENABLE has no effect on the conversion process. BYTE SELECT Input The BYTE SELECT input selects the byte of the position data to be presented at the data output DB1 to DB8. The least sig- nificant byte will be presented on data output DB9 to DB16 (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S83 is used with a resolution less than 16 bits the unused data lines are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data output DB1 and DB8. A logic “LO” will present the least sig- nificant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will duplicate data outputs 9 to 16. The operation of the BYTE SELECT has no effect on the con- version process of the converter. RIPPLE CLOCK As the output of the converter passes through the major carry, i.e., all “1s” to all “0s” or the converse, a positive going edge on the RIPPLE CLOCK (RC) output is initiated indicating that a revolution, or a pitch, of the input has been completed. The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE CLOCK is normally set high before a BUSY pulse and resets before the next positive going edge of the next BUSY pulse. The only exception to this is when DIR changes while the RIPPLE CLOCK is high. Resetting of the RIPPLE clock will only occur if the DIR remains stable for two consecutive posi- tive BUSY pulse edges. If the AD2S83 is being used in a pitch and revolution counting application, the ripple and busy will need to be gated to prevent false decrement or increment (see Figure 2). RIPPLE CLOCK is unaffected by INHIBIT. 5V 5K1 IN4148 BUSY IN4148 RIPPLE CLOCK 2N3904 0V 10k 1k 5V TO COUNTER (CLOCK) NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW. Figure 2. Diode Transistor Logic N and Gate |
Nº de peça semelhante - AD2S83_15 |
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Descrição semelhante - AD2S83_15 |
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