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AD1376 Folha de dados(PDF) 7 Page - Analog Devices |
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AD1376 Folha de dados(HTML) 7 Page - Analog Devices |
7 / 12 page AD1376/AD1377 Rev. D | Page 7 of 12 In either adjustment circuit, the fixed resistor connected to Pin 27 should be located close to this pin to keep the pin connection short. Pin 27 is quite sensitive to external noise pickup and should be guarded by ANALOG COMMON. TIMING The timing diagram is shown in Figure 8. Receipt of a CONVERT START signal sets the STATUS flag, indicating conversion in progress. This in turn removes the inhibit applied to the gated clock, permitting it to run through 17 cycles. All the SAR parallel bits, the STATUS flip-flops, and the gated clock inhibit signal are initialized on the trailing edge of the CONVERT START signal. At time t0, B1 is reset and B2–B16 are set unconditionally. At t1, the Bit 1 decision is made (keep) and Bit 2 is reset unconditionally. This sequence continues until the Bit 16 (LSB) decision (keep) is made at t16. The STATUS flag is reset, indicating that the conversion is complete and that the parallel output data is valid. Resetting the STATUS flag restores the gated clock inhibit signal, forcing the clock output to the low Logic 0 state. Note that the clock remains low until the next conversion. Corresponding parallel data bits become valid on the same positive-going clock edge. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 (3) (2) (1) 0 1 10 0 1 11 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 0 MSB STATUS INTERNAL CLOCK CONVERT START BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 LSB LSB MSB MAXIMUM THROUGHPUT TIME CONVERSION TIME (2) NOTES: 1. THE CONVERT START PULSEWIDTH IS 50ns MIN AND MUST REMAIN LOW DURING A CONVERSION. THE CONVERSION IS INITIATED BY THE TRAILING EDGE OF THE CONVERT COMMAND. 2. MSB DECISION. 3. CLOCK REMAINS LOW AFTER LAST BIT DECISION. Figure 8. Timing Diagram (Binary Code 0110011101111010) DIGITAL OUTPUT DATA Parallel data from TTL storage registers is in negative true form (Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding is complementary binary for unipolar ranges and complement- tary offset binary for bipolar ranges. Parallel data becomes valid at least 20 ns before the STATUS flag returns to Logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the STATUS flag (see Figure 9). Parallel data output changes state on positive going clock edges. BIT 16 VALID BUSY (STATUS) 20ns MIN TO 90ns Figure 9. LSB Valid to Status Low Short Cycle Input Pin 32 (SHORT CYCLE) permits the timing cycle shown in Figure 8 to be terminated after any number of desired bits has been converted, allowing somewhat shorter conversion times in applications not requiring full 16-bit resolution. When 10-bit resolution is desired, Pin 32 is connected to Bit 11 output Pin 11. The conversion cycle then terminates and the STATUS flag resets after the Bit 10 decision (Figure 8). Short cycle connections and associated 8-, 10-, 12-, 13-, 14-, and 15-bit conversion times are summarized in Table 3 for a 1.6 MHz clock (AD1377) or 933 kHz clock (AD1376). Table 3. Short Cycle Connections Resolution Maximum Conversion Time (µs) Bits (% FSR) AD1377 AD1376 Status Flag Reset Connect Short Cycle Pin 32 to 16 0.0015 10 17.1 t16 NC (Open) 15 0.003 9.4 16.1 t15 Pin 16 14 0.006 8.7 15.0 t1 Pin 15 13 0.012 8.1 13.9 t13 Pin 14 12 0.024 7.5 12.9 t12 Pin 13 10 0.100 6.3 10.7 t10 Pin 11 8 0.390 5.0 8.6 t8 Pin 9 INPUT SCALING The ADC inputs should be scaled as close to the maximum input signal range as possible to use the maximum signal resolution of the ADC. Connect the input signal as shown in Table 4. See Figure 10 for circuit details. |
Nº de peça semelhante - AD1376_15 |
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Descrição semelhante - AD1376_15 |
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