Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

AD1555 Folha de dados(PDF) 10 Page - Analog Devices

Nome de Peças AD1555
Descrição Electrónicos  24-Bit ADC with Low Noise PGA
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD1555 Folha de dados(HTML) 10 Page - Analog Devices

Back Button AD1555_15 Datasheet HTML 6Page - Analog Devices AD1555_15 Datasheet HTML 7Page - Analog Devices AD1555_15 Datasheet HTML 8Page - Analog Devices AD1555_15 Datasheet HTML 9Page - Analog Devices AD1555_15 Datasheet HTML 10Page - Analog Devices AD1555_15 Datasheet HTML 11Page - Analog Devices AD1555_15 Datasheet HTML 12Page - Analog Devices AD1555_15 Datasheet HTML 13Page - Analog Devices AD1555_15 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 24 page
background image
REV. B
AD1555/AD1556
–10–
AD1555 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
AGND1
Analog Ground
2
PGAOUT
Programmable Gain Amplifier Output. The output of the on-chip programmable gain amplifier is
available at this pin. Refer to Table III for PGA gain settings selection.
3, 26
+VA
Positive Analog Supply Voltage. +5 V nominal.
4, 20, 21
–VA
Negative Analog Supply Voltage. –5 V nominal.
5
AIN(+)
Mux Input. Noninverting signal to the PGA mux input. Refer to Table III for input selection.
6
AIN(–)
Mux Input. Inverting signal to the PGA mux input. Refer to Table III for input selection.
7
TIN(+)
Mux Input. Noninverting test signal to the PGA mux input. Refer to Table III for input selection.
8
TIN(–)
Mux Input. Inverting test signal to the PGA mux input. Refer to Table III for input selection.
9NCPin for Factory Use Only. This pin must be kept not connected for normal operation.
10–14
CB0–CB4
Modulator Control. These input pins control the mux selection, the PGA gain settings, and the
standby modes of the AD1555. When used with the AD1556, these pins are generally directly tied
to the CB0–CB4 output pins of the AD1556. CB0–CB2 are generally used to set the PGA gain or
cause it to enter in the PGA standby mode (refer to Table III). CB3 and CB4 select the mux input
voltage applied to the PGA as described in Table III.
15
MFLG
Modulator Error. Digital output that is pulsed high if an overrange condition occurs in the modulator.
16
DGND
Digital Ground
17
MDATA
Modulator Output. The bitstream generated by the modulator is output in a return-to-zero data
format. The data is valid for approximately one-half a MCLK cycle. Refer to Figure 3.
18
MCLK
Clock Input. The clock input signal, nominally 256 kHz, provides the necessary clock for the
Σ-∆
modulator. When this input is static, AD1555 is in the power-down mode.
19
VL
Positive Digital Supply Voltage. 5 V Nominal.
22
AGND3
Analog Ground. Used as the ground reference for the REFIN pin.
23
REFCAP1
DAC Reference Filter. The reference input is internally divided and available at this pin to provide
the reference for the
-
modulator. Connect an external 22
µF (5 V min) tantalum capacitor from
REFCAP1 to AGND3 to filter the external reference noise.
24
REFCAP2
Reference Filter. The reference input is internally divided and available at this pin.
25
REFIN
Reference Input. This input accepts a 3 V level that is internally divided to provide the reference for
the
Σ-∆ modulator.
27
AGND2
Analog Ground.
28
MODIN
Modulator Input. Analog input to the modulator. Normally, this input is directly tied to
PGAOUT output.
AD1556 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1, 21, 27, 28,
NC
No Connect
33
2–6
PGA0–PGA4
PGA and MUX Control Inputs. Sets the logic level of CB0-CB4 output pins respectively and the
state of the corresponding bit in the configuration register upon RESET or when in hardware mode.
Refer to Table III.
7–9
BW0–BW2
Output Rate Control Inputs. Sets the digital filter decimation rate and the state of the correspond-
ing bit in the configuration register upon RESET or when in hardware mode. Refer to the Filter
Specifications and Table VI.
10
H/
S
Hardware/Software Mode Select. Determines how the device operation is controlled. In hardware
mode, H/
S is high, the state of hardware pins set the mode of operation. When H/S is low, a write
sequence to the Configuration Register or a previous write sequence sets the device operation.
11, 22, 44
VL
Positive Digital Supply Voltage. 3.3 V or 5 V nominal.
12, 23, 24, 34
DGND
Digital Ground
13
SCLK
Serial Data Clock. Synchronizes data transfer to either write data on the DIN input pin or read
data on the DOUT output pin.


Nº de peça semelhante - AD1555_15

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
Analog Devices
AD1555-AD1556 AD-AD1555-AD1556 Datasheet
429Kb / 24P
   24-Bit ADC WITH LOW NOISE PGA
REV. B
AD1555/56-REF AD-AD1555/56-REF Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555AP AD-AD1555AP Datasheet
429Kb / 24P
   24-Bit ADC WITH LOW NOISE PGA
REV. B
AD1555AP AD-AD1555AP Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD1555APRL AD-AD1555APRL Datasheet
429Kb / 24P
   24-Bit ADC WITH LOW NOISE PGA
REV. B
More results

Descrição semelhante - AD1555_15

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
Analog Devices
AD1556 AD-AD1556_15 Datasheet
435Kb / 24P
   24-Bit ADC with Low Noise PGA
REV. B
AD1555 AD-AD1555 Datasheet
429Kb / 24P
   24-Bit ADC WITH LOW NOISE PGA
REV. B
AD1555APZRL AD-AD1555APZRL Datasheet
435Kb / 24P
   24-Bit - ADC with Low Noise PGA
REV. B
AD7190 AD-AD7190 Datasheet
178Kb / 21P
   4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
Rev.PrD 7/08
AD7193 AD-AD7193_17 Datasheet
1Mb / 57P
   24-Bit Sigma-Delta ADC with PGA
AD7194 AD-AD7194_17 Datasheet
1Mb / 55P
   24-Bit Sigma-Delta ADC with PGA
AD7190 AD-AD7190_08 Datasheet
749Kb / 40P
   4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
REV. 0
AD7192 AD-AD7192 Datasheet
711Kb / 40P
   4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
REV. A
AD7124-4 AD-AD7124-4 Datasheet
1Mb / 90P
   4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
AD7124-8 AD-AD7124-8 Datasheet
1Mb / 91P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Folha de dados Download

Go To PDF Page


Ligação URL




Privacy Policy
ALLDATASHEETPT.COM
ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com