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AD1556 Folha de dados(PDF) 5 Page - Analog Devices

Nome de Peças AD1556
Descrição Electrónicos  24-Bit ADC with Low Noise PGA
Download  24 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD1556 Folha de dados(HTML) 5 Page - Analog Devices

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REV. B
–5–
AD1555/AD1556
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
CLKIN Frequency
1
fCLKIN
0.975
1.024
1.075
MHz
CLKIN Duty Cycle Error
45
55
%
MCLK Output Frequency
1
fCLKIN/4
SYNC Setup Time
t1
10
ns
SYNC Hold Time
t2
10
ns
CLKIN Rising to MCLK Output Falling on SYNC
t3
20
ns
CLKIN Falling to MCLK Output Rising
t4
20
ns
CLKIN Falling to MCLK Output Falling
t5
20
ns
MCLK Input Falling to MDATA Falling
t6
30
ns
MCLK Input Rising to MDATA and MFLG Valid
t7
100
ns
TDATA Setup Time after SYNC
t8
5ns
TDATA Hold Time
t9
5ns
RESET Setup Time
t10
15
ns
RESET Hold Time
t11
15
ns
CLKIN Falling to DRDY Rising
t12
20
ns
CLKIN Rising to DRDY Falling
2
t13
20
ns
CLKIN Rising to
ERROR Falling
t14
50
ns
RSEL to Data Valid
t15
25
ns
RSEL Setup to SCLK Falling
t16
10
ns
DRDY to Data Valid
t17
25
ns
DRDY High Setup to SCLK Falling
t18
10
ns
R/
W to Data Valid
t19
25
ns
R/
W High Setup to SCLK Falling
t20
10
ns
CS to Data Valid
t21
25
ns
CS Low Setup to SCLK Falling
t22
10
ns
SCLK Rising to DOUT Valid
t23
25
ns
SCLK High Pulsewidth
t24
25
ns
SCLK Low Pulsewidth
t25
25
ns
SCLK Period
t26
70
ns
SCLK Falling to DRDY Falling
2
t27
20
ns
CS High or R/W Low to DOUT Hi-Z
t28
20
ns
R/
W Low Setup to SCLK Falling
t29
10
ns
CS Low Setup to SCLK Falling
t30
10
ns
Data Setup Time to SCLK Falling
t31
10
ns
Data Hold Time after SCLK Falling
t32
10
ns
R/
W Hold Time after SCLK Falling
t33
10
ns
NOTES
1The gain of the modulator is proportional to f
CLKIN and MCLK frequency.
2With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor.
Specifications subject to change without notice.
(+VA = +5 V
5%; –VA = –5 V
5%; AD1555 VL = 5 V
5%, AD1556 VL = 2.85 V to 5.25 V;
CLKIN = 1.024 MHz; AGND = DGND = 0 V; CL = 50 pF; TA = TMIN to TMAX, unless otherwise noted)
IOH
IOL
TO OUTPUT
PIN
1.4V
CL
50pF
500 A
1.6mA
Figure 2. Load Circuit for Digital Interface Timing


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