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CD4517 Folha de dados(PDF) 1 Page - Intersil Corporation

Nome de Peças CD4517
Descrição Electrónicos  CMOS Dual 64-Stage Static Shift Register
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Fabricante Electrônico  INTERSIL [Intersil Corporation]
Página de início  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4517 Folha de dados(HTML) 1 Page - Intersil Corporation

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4517BMS
CMOS Dual 64-Stage
Static Shift Register
Pinout
CD4517BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q16A
Q48A
WEA
CLA
Q64A
Q32A
VSS
DA
VDD
Q48B
WEB
CLB
Q64B
Q32B
DB
Q16B
Features
• High-Voltage Types (20-Volt Rating)
• Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V
• Clock Frequency 12MHz (Typ.) at VDD = 10V
• Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock
Rise and Fall Times
• Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load, or Two HTL Loads
• 3-State Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V, and 15V Parametric Ratings
• Meets all Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of ‘B’ Series CMOS
Devices"
Applications
• Time-delay Circuits
• Scratch-pad Memories
• General-purpose Serial Shift-register Applications
December 1992
File Number
3341
Functional Diagram
CL
D1
Q16
16 STAGES
STAGE 16
OUT/IN TAP
CL
D17
Q32
16 STAGES
STAGE32
OUT/IN TAP
CL
D33
Q48
16 STAGES
STAGE 48
OUT/IN TAP
CL
D49
Q64
16 STAGES
STAGE 64
OUT/IN TAP
CL
D
WE = 0
WE = 1
WE
Description
CD4517BMS
dual
64-stage
static
shift
register consists of two independent registers
each having a clock, data, and write enable
input and outputs accessible at taps following
the 16th, 32rd, 48th, and 64th stages. These
taps also serve as input points allowing data
to be inputted at the 17th, 33rd, and 49th
stages when the write enable input is a logic
1 and the clock goes through a low-to-high
transition. The truth table indicates how the
clock and write enable inputs control the
opeation of the CD4517BMS. Inputs at the
intermediate taps allow entry of 64 bits into
the register with 16 clock pulses. The 3-state
outputs permit connection of this device to an
external bus.
The CD4517BMS is supplied in these 16 lead
outline packages:
Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack
H6P


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