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LF3310QC15 Folha de dados(PDF) 5 Page - LOGIC Devices Incorporated |
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LF3310QC15 Folha de dados(HTML) 5 Page - LOGIC Devices Incorporated |
5 / 21 page DEVICES INCORPORATED Video Imaging Products 5 LF3310 Horizontal / Vertical Digital Image Filter 11/08/2001-LDS.3310-H HRSL3-0 — Horizontal Round/Select/ Limit Control HRSL3-0 determines which of the sixteen user-programmable Round/ Select/Limit registers (RSL registers) are used in the horizontal Round/ Select/Limit circuitry (RSL circuitry). A value of 0 on HRSL3-0 selects RSL register 0. A value of 1 selects round/select/limit register 1 and so on. HRSL3-0 is latched on the rising edge of CLK (see the horizontal round, select, and limit sections for a complete discussion). VRSL3-0 —Vertical Round/Select/Limit Control VRSL3-0 determines which of the sixteen user-programmable RSL registers are used in the vertical RSL circuitry. A value of 0 on VRSL3-0 selects RSL register 0. A value of 1 selects RSL register 1 and so on. VRSL3-0 is latched on the rising edge of CLK (see the vertical round, select, and limit sections for a com- plete discussion). OE — Output Enable When OE is LOW, DOUT11-0 is enabled for output. When OE is HIGH, DOUT11-0 is placed in a high-impedance state. HPAUSE — LF InterfaceTM Pause When HPAUSE is HIGH, the Hori- zontal LF InterfaceTM loading sequence is halted until HPAUSE is returned to a LOW state. This effectively allows the user to load coefficients and Control Registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). VPAUSE — LF InterfaceTM Pause When VPAUSE is HIGH, the Vertical LF InterfaceTM loading sequence is halted until VPAUSE is returned to a LOW state. This effectively allows the user to load coefficients and Control Registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). OPERATIONAL MODES Dimensionally Separate In Dimensionally Separate Mode, the horizontal and vertical filters are cascaded together to form a two-dimensional image filter (see Figures 4 and 5). Bit 1 in Configura- tion Register 4 determines the cascade order. If this bit is set to “0”, data on DIN11-0 is fed into the horizontal filter first. The horizontal filter then feeds data into the vertical filter. If this bit is set to “1”, data on DIN11-0 is fed into the vertical filter first. The vertical filter then feeds data into the horizontal filter. Orthogonal In Orthogonal Mode, the horizontal and vertical filters are used concur- rently to implement an orthogonal kernel on the input data (see Figure 6). DIN11-0 HORIZONTAL FILTER LINE BUFFER 12 12 LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER DOUT11-0 12 FIGURE 4. DIMENSIONALLY SEPARATE MODE: H TO V DIN11-0 HORIZONTAL FILTER LINE BUFFER 12 LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER DOUT11-0 12 12 FIGURE 5. DIMENSIONALLY SEPARATE MODE: V TO H |
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Descrição semelhante - LF3310QC15 |
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