DEVICES INCORPORATED

Video Imaging Products

7

LF3330

Vertical Digital Image Filter

11/08/2001–LDS.3330-M

CONFIGURATION REGISTER

CLK

LD

W2

W1: Configuration Register loaded with new data on this rising clock edge.

PAUSE

SELECT REGISTER

W1

W2: Select Register loaded with new data on this rising clock edge.

Limiting

An output limiting function is

provided for the output of the

filter. The limit registers deter-

mine the valid range of output

values when limiting is enabled

(Bit 0 in Configuration Register 2).

There are sixteen 32-bit limit

which limit register is used during

the limit operation. A value of 0

A value of 1 selects limit register 1

and so on. Each limit register

contains both an upper and lower

limit value. If the value fed to the

limiting circuitry is less than the

lower limit, the lower limit value

is passed as the filter output. If

the value fed to the limiting

circuitry is greater than the upper

limit, the upper limit value is

may be changed every clock cycle

if desired. This allows the limit

range to be changed every clock

cycle. This is useful when filtering

interleaved data. When loading

limit values into the device, the

upper limit must be greater than

the lower limit. Limit register

loading is discussed in the LF

Coefficient Banks

The coefficient banks store the

coefficients which feed into the

multipliers in the filter. There is a

separate bank for each multiplier.

Each bank can hold 256 12-bit

coefficients. The banks are loaded

bank loading is discussed in the

Configuration and Control Registers

The configuration registers deter-

mine how the LF3330 operates.

Tables 2 through 5 show the formats

of the four configuration registers.

There are three types of control

registers: round, select, and limit.

There are sixteen round registers.

Each round register is 32 bits wide.

register is used for rounding.

There are sixteen select registers.

Each select register is 5 bits wide.

register is used for the select cir-

cuitry.

There are sixteen limit registers.

Each limit register is 32 bits wide

and stores both an upper and lower

limit value. The lower limit is

stored in bits 15-0 and the upper

COEFFICIENT SET 1

CLK

PAUSE

LD

W1: Configuration Register loaded with new data on this rising clock edge.

W1