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8T73S1802 Folha de dados(PDF) 11 Page - Integrated Device Technology

Nome de Peças 8T73S1802
Descrição Electrónicos  High-performance fanout buffer clock and fanout buffer
Download  24 Pages
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Fabricante Electrônico  IDT [Integrated Device Technology]
Página de início  http://www.idt.com
Logo IDT - Integrated Device Technology

8T73S1802 Folha de dados(HTML) 11 Page - Integrated Device Technology

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REVISION 1 08/31/15
11
1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
8T73S1802 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset from Carrier Frequency (Hz)
Additive Phase Jitter @ 250MHz
12kHz to 20MHz = 79fs (typical)


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