8T74S208A-01 datasheet(2/19 Pages) IDT

Nome de Peças	8T74S208A-01

Descrição Electrónicos	One differential input reference clock

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8T74S208A-01 DATA SHEET

2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER

2

REVISION 1 06/15/15

Pin Descriptions and Pin Characteristics

Table 1. Pin Descriptions1

NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Number

Name

Type

Description

1

ADR1

Input

Pulldown

I2C Address input. LVCMOS/LVTTL interface levels.

2

GND

Power

Ground pin.

3Q0

Output

Differential output pair 0. LVDS interface levels.

4

nQ0

Output

5Q1

Output

Differential output pair 1. LVDS interface levels.

6

nQ1

Output

7

GND

Power

Ground pin.

8

VDDO

Power

Output supply pin.

9Q2

Output

Differential output pair 2. LVDS interface levels.

10

nQ2

Output

11

Q3

Output

Differential output pair 3. LVDS interface levels.

12

nQ3

Output

13

Q4

Output

Differential output pair 4. LVDS interface levels.

14

nQ4

Output

15

Q5

Output

Differential output pair 5. LVDS interface levels.

16

nQ5

Output

17

VDDO

Power

Output supply pin.

18

GND

Power

Ground pin.

19

Q6

Output

Differential output pair 6. LVDS interface levels.

20

nQ6

Output

21

Q7

Output

Differential output pair 7. LVDS interface levels.

22

nQ7

Output

23

GND

Power

Ground pin.

24

FSEL0

Input

Pulldown

Frequency divider select control. See Table 3A for function.



LVCMOS/LVTTL interface levels.

25

FSEL1

Input

Pulldown

Frequency divider select control. See Table 3A for function.



LVCMOS/LVTTL interface levels.

26

IN

Input

Non-inverting differential clock input. RT = 50

 termination to V

T.

27

VT

Termination

Input

Input for termination. Both IN and nIN inputs are internally terminated 50



to this pin. See input termination information in the applications section.

28

nIN

Input

Inverting differential clock input. RT = 50

 termination to V

T.

29

VDD

Power

Power supply pin.

30

SDA

I/O

Pullup

I2C Data Input/Output. Input. LVCMOS/LVTTL interface levels.



Output: open drain.

31

SCL

Input

Pullup

I2C Clock Input. LVCMOS/LVTTL interface levels.

32

ADR0

Input

Pulldown

I2C Address input. LVCMOS/LVTTL interface levels.

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