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8V79S674 Folha de dados(PDF) 11 Page - Integrated Device Technology |
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11 / 21 page 8V79S674 DATA SHEET REVISION 2 04/10/15 11 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 3.3V LVPECL Input with Built-In 50 Termination Interface The IN /nIN with built-in 50 terminations accept LVDS, LVPECL, CML and other differential signals. Both VOH and VOL must meet the VIN and VIH input requirements. Figures 2A to 2D show interface examples for the IN /nIN input with built-in 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 2A. IN/nIN Input with Built-In 50 Driven by an LVDS Driver Figure 2C. IN/nIN Input with Built-In 50 Driven by a CML Driver with Open Collector Figure 2B. IN/nIN Input with Built-In 50 Driven by an LVPECL Driver Figure 2D. IN/nIN Input with Built-In 50 Driven by a CML Driver with Built-In 50 Pullup C1 C2 VT V_REF_AC 50 Ω 50 Ω 3.3V CML with Built-In Pullup 3.3V IN nIN 3.3V Receiver with Built-In 50 Ω Zo = 50 Ω Zo = 50 Ω |
Nº de peça semelhante - 8V79S674 |
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Descrição semelhante - 8V79S674 |
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